Multi-chip package capable of testing internal signal lines

• US 10,497,670 B2
• Filed: 07/21/2017
• Issued: 12/03/2019
• Est. Priority Date: 12/06/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Na, Dae-hoon, Kim, Hyun-jin, Lee, Jang-woo
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US15/656,071
• Publication Number:
  US 20180158799A1
• Time in Patent Office: 865 Days
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires.

Claims

1. A multi-chip package comprising:

a printed circuit board;

a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit and a plurality of pads; and

second semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first semiconductor chip via a plurality of internal signal lines, each of the internal signal lines being a bonding wire,

wherein the test circuit is configured to detect short-circuit between at least two of the plurality of internal signal lines that are respectively connected to at least two pads of the plurality of pads by (1) enabling circuits of the first semiconductor chip respectively connected to the plurality of pads contacting the plurality of internal signal lines, and (2) transmitting complementary data to the at least two pads.

2. The multi-chip package of claim 1, wherein

the plurality of pads contacting the plurality of internal signal lines comprise bonding pads.

3. The multi-chip package of claim 1, wherein the circuits connected to the at least two pads comprise output drivers configured to transmit data to the second semiconductor chips via the plurality of internal signal lines.

4. The multi-chip package of claim 3, wherein the test circuit comprises:

a path selection circuit configured to enable the output drivers; and

a pattern generator configured to provide complementary data to the output drivers, respectively.

5. The multi-chip package of claim 1, wherein the test circuit is configured to be activated in response to data applied to a data terminal from among external terminals of the multi-chip package.

6. The multi-chip package of claim 1, wherein the test circuit is configured to detect the short-circuit between the plurality of internal signal lines of a first branch contacting the plurality of pads of the first semiconductor chip.

7. The multi-chip package of claim 6, wherein the test circuit is configured to detect the short-circuit between the plurality of internal signal lines of a second branch contacting the plurality of pads of the second semiconductor chips.

8. The multi-chip package of claim 1, wherein

the multi-chip package comprises an embedded multimedia card (eMMC) device,

the second semiconductor chips comprise non-volatile memory devices, and

the first semiconductor chip comprises an eMMC controller configured to perform data communication between the second semiconductor chips and an eMMC host outside the multi-chip package.

9. The multi-chip package of claim 1, wherein

the multi-chip package comprises a universal flash storage (UFS) device,

the second semiconductor chips comprise non-volatile memory devices, and

the first semiconductor chip comprises a device controller configured to control a write, read, or erase operation of the second semiconductor chips.

10. A multi-chip package comprising:

a printed circuit board;

a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit, a first pad, and a second pad; and

second semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first semiconductor chip via a plurality of internal signal lines, each of the plurality of internal signal lines being a bonding wire,

wherein the test circuit is configured to detect short-circuit between at least two of the plurality of internal signal lines that are respectively connected to the first pad and the second pad by inverting one of a first data and a second data by (1) enabling first and second circuits of the first semiconductor chip that are connected to the first pad and the second pad thereof, respectively, each of which is connected to a corresponding one of the plurality of internal signal lines of the multi-chip package, (2) outputting the first data to the first pad through the first circuit, and (3) receiving the second data from the second pad through the second circuit.

11. The multi-chip package of claim 10, wherein

the first circuit comprises an output driver connected to the first pad, and

the second circuit comprises an input driver connected to the second pad.

12. The multi-chip package of claim 11, wherein the test circuit comprises:

a write path selection circuit configured to provide the first data to the output driver;

a read path selection circuit configured to receive the second data from the input driver;

a first switch configured to provide the first data of the write path selection circuit to a data inversion circuit;

a second switch configured to provide the second data of the read path selection circuit to the data inversion circuit; and

the data inversion circuit configured to invert one of the first and second data.

13. The multi-chip package of claim 12, wherein the test circuit is configured to be activated in response to data applied to a data terminal from among external terminals of the multi-chip package.

14. The multi-chip package of claim 10, wherein

the multi-chip package comprises an embedded multimedia card (eMMC) device,

the second semiconductor chips comprise non-volatile memory devices, and

the first semiconductor chip comprises an eMMC controller configured to perform data communication between the second semiconductor chips and an eMMC outside the multi-chip package.

15. The multi-chip package of claim 10, wherein

the multi-chip package comprises a universal flash storage (UFS) device,

the second semiconductor chips comprise non-volatile memory devices, and

the first semiconductor chip comprises a device controller configured to control a write, read, or erase operation of the second semiconductor chips.

16. A multi-chip package comprising:

a printed circuit board;

a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit, a plurality of pads including a first pad and a second pad, an input driver, and an output driver, the test circuit including,

a write path selection circuit configured to provide first data to the first pad, from among the plurality of pads, via the output driver,

a read path selection circuit configured to receive second data from the second pad, from among the plurality of pads, via the input driver,

a data inversion circuit configured to invert one of the first data and the second data,

a first switch configured to provide the first data of the write path selection circuit to the data inversion circuit, and

a second switch configured to provide the second data of the read path selection circuit to the data inversion circuit; and

second semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first pad and the second pad of the first semiconductor chip via a plurality of internal signal lines, each of the plurality of internal signal lines being a bonding wire,

wherein the test circuit is configured to detect short-circuit between at least two of the plurality of internal signal lines that are respectively connected to the first pad and the second pad by (1) enabling circuits of the first semiconductor chip respectively connected to the first pad and the second pad, and (2) transmitting complementary data to the first pad and the second pad.

17. The multi-chip package of claim 16, wherein

the first and second pads comprise bonding pads.

18. The multi-chip package of claim 16, wherein the test circuit is configured to be activated in response to data applied to a data terminal from among external terminals of the multi-chip package.

19. The multi-chip package of claim 16, wherein the test circuit is configured to detect the short-circuit between the plurality of internal signal lines of a first branch contacting the first pad and the second pad of the first semiconductor chip.

20. The multi-chip package of claim 16, wherein the test circuit is configured to detect the short-circuit of the plurality of internal signal lines of a second branch contacting the first pad and the second pad of the second semiconductor chips.