Phase locked loop, phase locked loop arrangement, transmitter and receiver and method for providing an oscillator signal

• US 10,498,343 B2
• Filed: 04/08/2016
• Issued: 12/03/2019
• Est. Priority Date: 04/08/2016
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Sjoland, Henrik, Pahlsson, Tony
• Primary Examiner(s): Aghdam, Freshteh N
• Application Number:
  US16/091,090
• Publication Number:
  US 20190131978A1
• Time in Patent Office: 1,334 Days
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H04L 5/0048 Allocation of pilot signals, i.e. of signals known to the receiver
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.

Claims

1. A phase locked loop for a beamforming system, comprising:

a digital loop filter configured to provide a digital control word to a digital controlled oscillator, said digital controlled oscillator configured to provide an oscillator signal in response to the digital control word;

a frequency divider configured to provide a first feedback signal and a second feedback signal in response to the oscillator signal, the second feedback signal delayed with respect to the first feedback signal;

a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator paths configured to provide a respective phase delay signal to the digital loop filter in response to a respective phase adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.

2. The phase locked loop according to claim 1, wherein each of the first and second comparator paths comprises:

a phase comparator configured to output a respective one of the phase control signals in response to the phase deviation;

an adjustable charge pump configured to provide the respective one of the phase delay signals to the digital loop filter in response to the phase control signal and the respective phase adjustment signal.

3. The phase locked loop according to claim 1, wherein the delay of the second feedback signal with respect to the first feedback signal is dependent on the frequency or period of the oscillator signal.

4. The phase locked loop according to claim 3, wherein the delay is an integer multiple of the half-period of the oscillator signal.

5. The phase locked loop according to claim 1, wherein a sum of an amplitude of the respective phase delay signals of the first and second comparator paths is kept substantially constant.

6. The phase locked loop according to claim 1, wherein a phase of the oscillator signal is substantially controlled by the amplitude of the phase delay signal of the second comparator path or by a portion of the digital control word derived from the phase delay signal of the second comparator path.

7. The phase locked loop according to claim 2, further comprising an adjustment circuit configured to adjust a ratio of amplitudes of the phase delay signals of the respective adjustable charge pump.

8. The phase locked loop according to claim 1, further comprising a combiner element for summing the respective phase delay signal from each of the comparator paths and to provide a summed phase delay signal to the digital loop filter.

9. The phase locked loop according to claim 1, wherein the frequency divider is an adjustable divider configured to divide a frequency of the oscillator signal based on a frequency divider word.

10. A phase locked loop arrangement for the beamforming system having at least two phase locked loops according to claim 1 and further comprising:

a reference signal source providing the reference signal and coupled to the first and second comparator paths of each of the at least two phase locked loops;

a phase deviation module configured to provide a phase control signal to each of the phase locked loops to generate a phase difference between oscillator signals of the at least two phase locked loops.

11. Transmitter arrangement, comprising:

the phase locked loop arrangement according to claim 10;

an antenna array having a plurality of antenna elements, wherein each of the antenna elements is in operative connection to a respective one of the phase locked loops of the phase locked loop arrangement to receive an individual signal for transmission derived from the respective oscillator signal thereof.

12. Receiver arrangement, comprising:

the phase locked loop arrangement according to claim 10;

an antenna array having a plurality of antenna elements, wherein each of the antenna elements is in operative connection to a respective one of the phase locked loops of the phase locked loop arrangement to down-convert a received signal with the respective oscillator signal thereof.

13. A method for providing an oscillator signal in a phase locked loop, comprising:

generating a common reference signal;

generating an oscillator signal in response to a digital control word;

generating a first feedback signal based on the oscillator signal and a second feedback signal based on the oscillator signal and delayed with respect to the first feedback signal;

generating a first phase delay signal based on a comparison between the reference signal and the first feedback signal and a second phase delay signal based on a comparison between the reference signal and the second feedback signal;

adjusting a ratio between the first and second phase delay signals;

generating the digital control word based on the adjusted phase delay ratio of first and second phase delay signals.

14. The method according to claim 13, wherein generating the second feedback signal comprises delaying the first feedback signal depending on the frequency or period of the oscillator signal.

15. The method according to claim 14, wherein the delay is an integer multiple of a half-period of the output signal.

16. The method according to claim 13, wherein a sum of the first and the second phase delay signals is kept substantially constant.

17. The method according to claim 13, wherein a phase of the oscillator signal is adjusted by a portion of the digital control word derived from the second phase delay signal.

18. The method according to claim 13, wherein adjusting the ratio comprises adjusting a respective amplitude of at least one of the first and second current signals.

19. The method according to claim 13, wherein generating the digital control word comprises combining the first and second phase delay signals and filtering the combined phase delay signals.