GOA unit and driving method thereof, GOA circuit, display device

• US 10,504,447 B2
• Filed: 09/20/2017
• Issued: 12/10/2019
• Est. Priority Date: 03/20/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Chengdu BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Lan, Chuanyan, Kim, Taehyun
• Primary Examiner(s): Michaud, Robert J
• Application Number:
  US15/769,058
• Publication Number:
  US 20190066597A1
• Time in Patent Office: 811 Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2330/026 Arrangements or methods related to booting a display
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes

Abstract

The present disclosure provides a GOA unit of a light emitting control signal and its driving method, a GOA circuit and display device, relating to the field of display technology. And they can overcome the problems of a screen flickering or an abnormal display that the display device may have. The GOA unit of the light emitting control signal includes a potential control module, a pull-down module, a pull-up module and a writing module. The writing module is connected to a second voltage terminal, a signal control terminal, a signal output terminal, and outputs the voltage of the second voltage terminal to the signal output terminal.

Claims

1. A GOA unit of a light emitting control signal, comprising a potential control module, a pull-up module, a pull-down module and a writing module;

the potential control module being connected to a first voltage terminal, a second voltage terminal, a first clock signal terminal, a second clock signal terminal, a signal input terminal and a first node, respectively; and

being configured to output the signal from the second voltage terminal to the first node under control of the first clock signal terminal and the first voltage terminal; and

/or to output the signal from the second clock signal terminal to the first node under control of the first clock signal terminal, the first voltage terminal and the signal input terminal;

the pull-down module being connected to the first node, the first voltage terminal, the second voltage terminal, the first clock signal terminal, the second clock signal terminal and a signal output terminal, respectively; and

being configured to output the signal from the first voltage terminal to the signal output terminal under control of the first node, the first voltage terminal, the second voltage terminal, the first clock terminal and the second clock signal terminal;

the pull-up module being connected to the first node, the second voltage terminal and the signal output terminal, respectively; and

being configured to output the signal from the second voltage terminal to the signal output terminal under control of the first node;

the writing module being connected to the second voltage terminal, a signal control terminal and the signal output terminal, respectively; and

being configured to output the voltage of the second voltage terminal to the signal output terminal under control of the signal control terminal;

wherein, the potential control module comprises a pull-up control module and a pull-down control module;

the pull-up control module is connected to the pull-down control module, the first clock signal terminal, the first voltage terminal, the second voltage terminal and the first node, respectively, and is configured to output the signal from the second voltage terminal to the first node under the control of the first clock signal terminal and the first voltage terminal; and

the pull-down control module is connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first voltage terminal and the first node, respectively, and is configured to output the signal from the second clock signal terminal to the first node under the control of the signal input terminal, the first clock signal terminal and the first voltage terminal;

wherein, the pull-down control module comprises a sixth transistor, a seventh transistor, an eighth transistor and a second capacitor;

a gate of the sixth transistor is connected to the first clock signal terminal, a first electrode of the sixth transistor is connected to the signal input terminal, and a second electrode of the sixth transistor is connected to a first electrode of the seventh transistor;

a gate of the seventh transistor is connected to the first voltage terminal, and a second electrode of the seventh transistor is connected to a gate of the eighth transistor;

a first electrode of the eighth transistor is connected to the second clock signal terminal, and a second electrode of the eighth transistor is connected the first node; and

a first end of the second capacitor is connected to the gate of the eighth transistor, and a second end of the second capacitor is connected to the second electrode of the eighth transistor.

2. The GOA unit according to claim 1, wherein, the writing module comprises a first transistor;

a gate of the first transistor is connected to the signal control terminal, a first electrode of the first transistor is connected to the second voltage terminal, and a second electrode of the first transistor is connected to the signal output terminal.

3. The GOA unit according to claim 1, wherein, the pull-up control module comprises a second transistor, a third transistor and a first capacitor;

a gate of the second transistor is connected to the first clock signal terminal, a first electrode of the second transistor is connected to the first voltage terminal, and a second electrode of the second transistor is connected to a gate of the third transistor;

a first electrode of the third transistor is connected to the second voltage terminal, a second electrode of the third transistor is connected to the first node;

a first end of the first capacitor is connected to the second voltage terminal, and a second end of the first capacitor is connected to the gate of the third transistor.

4. The GOA unit according to claim 3, wherein, the pull-up control module is further connected to the second clock signal terminal, and the pull-up control module further comprises a fourth transistor and a fifth transistor;

a gate of the fourth transistor is connected to the second electrode of the second transistor, a first electrode of the fourth transistor is connected to the second voltage terminal, and a second electrode of the fourth transistor is connected to a first electrode of the fifth transistor;

a gate of the fifth transistor is connected to the second clock signal terminal, a second electrode of the fifth transistor is connected to the pull-down control module.

5. The GOA unit according to claim 1, wherein, the pull-down control module further comprises a ninth transistor;

a gate of the ninth transistor is connected to the second electrode of the sixth transistor, a first electrode of the ninth transistor is connected to the first clock signal terminal, and a second electrode of the ninth transistor is connected to the pull-up control module.

6. The GOA unit according to claim 1, wherein, the pull-down module comprises a tenth transistor, an eleventh transistor, a twelfth transistor and a third capacitor;

a gate of the tenth transistor is connected to the first clock signal terminal, a first electrode of the tenth transistor is connected to the first voltage terminal, and a second electrode of the tenth transistor is connected to a gate of the twelfth transistor;

a gate of the eleventh transistor is connected to the first node, a first electrode of the eleventh transistor is connected to the second voltage terminal, and a second electrode of the eleventh transistor is connected to the gate of the twelfth transistor;

a first electrode of the twelfth transistor is connected to the first voltage terminal, and a second electrode of the twelfth transistor is connected to the signal output terminal;

a first end of the third capacitor is connected to the second clock signal terminal, and a second end of the third capacitor is connected to the gate of the twelfth transistor.

7. The GOA unit according to claim 1, wherein, the pull-up module comprises a thirteenth transistor;

a gate of the thirteenth transistor is connected to the first node, a first electrode of the thirteenth transistor is connected to the second voltage terminal, and a second electrode of the thirteenth transistor is connected to the signal output terminal.

8. A driving method for a GOA unit of the light emitting control signal according to claim 1, comprising:

within the first N image frames, the writing module writes the signal from the second voltage terminal to the signal output terminal under control of the signal control terminal;

from the image frame N+1, at the buffer stage of an image frame, the first clock signal terminal is input with a first voltage, the signal input terminal is input with the first voltage, the second clock signal is input with a second voltage; and

the potential control module outputs the signal from the second voltage terminal to the first node under the control of the first voltage terminal and the first voltage input to the first clock signal terminal, and outputs the second voltage input to the second clock signal terminal to the first node under the control of the first voltage input to the first clock signal terminal, the first voltage terminal and the first voltage input to the signal input terminal;

the pull-down module outputs the signal from the first voltage terminal to the signal output terminal under control of the first node, the first voltage terminal, the second voltage terminal, the first voltage input to the first clock signal terminal and the second voltage input to the second clock signal terminal;

at the pull-up stage of an image frame, the second clock signal terminal is input with the first voltage, the first clock signal terminal is input with the second voltage, the signal input terminal is input with the second voltage; and

the potential control module outputs the first voltage input to the second clock signal terminal to the first node under the control of the second voltage input to the first clock signal terminal, the first voltage terminal and the second voltage input to the signal input terminal;

the pull-up module outputs the signal of the second voltage terminal to the signal output terminal under the control of the first node;

at the pull-down stage of an image frame, the first clock signal terminal is input with the first voltage, the second clock signal terminal is input with the second voltage, the signal input terminal is input with the second terminal, and the potential control module outputs the signal from the second voltage terminal to the first node under control of the first voltage terminal and the first voltage input to the first clock signal terminal;

the pull-down module outputs the signal from the first voltage terminal to the signal output terminal under control of the first node, the first voltage terminal, the second voltage terminal, the first voltage input to the first clock signal terminal and the second voltage input to the second clock signal terminal;

wherein, N is a positive integer greater than or equal to 1.

9. A GOA circuit, comprising multiple cascaded GOA units of the light emitting control signal according to claim 1.

10. A display device, comprising the GOA circuit according to claim 9.