Positive logic switch with selectable DC blocking circuit
First Claim
1. A stack of FET switches, at least one FET switch requiring a negative VGS to turn OFF and configured so as to not require a negative power supply, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts.
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Accused Products
Abstract
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
520 Citations
18 Claims
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1. A stack of FET switches, at least one FET switch requiring a negative VGS to turn OFF and configured so as to not require a negative power supply, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts.
- 2. A stack of FET switches, including at least one positive-logic FET requiring a negative VGS to turn OFF and configured so as to not require a negative power supply, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts.
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5. A FET switch stack, including:
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(a) one or more positive-logic FETs requiring a negative VGS to turn OFF and configured so as to not require a negative power supply; and (b) a first end-cap FET that turns OFF when the VGS of the first end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification