Active matrix organic light emitting diode back plate for display device and method for manufacturing the same

• US 10,510,815 B2
• Filed: 12/21/2017
• Issued: 12/17/2019
• Est. Priority Date: 04/26/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Liu, Wei
• Primary Examiner(s): Hoang, Quoc D
• Application Number:
  US15/851,148
• Publication Number:
  US 20180315805A1
• Time in Patent Office: 726 Days
• CPC Class Codes: H10K 50/15 Hole transporting layers
• CPC Class Codes: H10K 50/816 Multilayers, e.g. transparent multilayers
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs

Abstract

The present disclosure provides an AMOLED back plate and a method for manufacturing the same. The manufacturing method includes: forming source and drain electrodes and a first via hole on a substrate having a light shielding layer and a buffer layer formed thereon, by a patterning process; depositing an active layer film and a gate insulating layer film sequentially, and forming an active layer, a gate insulating layer and a second via hole by a patterning process, wherein the active layer connected with the light shielding layer by the first via hole; forming a gate electrode and a transparent anode sequentially, wherein the transparent anode is arranged in a light emitting area and connected with one of the source and drain electrodes through the second via hole.

Claims

1. A method for manufacturing an AMOLED back plate, comprising:

forming source and drain electrodes on a substrate having a light shielding layer and a buffer layer covering the light shielding layer formed thereon, by a patterning process, wherein the source and drain electrodes are on the buffer layer;

depositing an active layer film and a gate insulating layer film sequentially, and forming an active layer, a gate insulating layer and a second via hole by a patterning process, wherein the active layer covers at least a part of a s urface of the source and drain electrodes, the surface being at a side of the source and drain electrodes which is farther away from the substrate, and the gate insulating layer is on the active layer; and

forming a gate electrode and a transparent anode sequentially, wherein the transparent anode is arranged in a light emitting area and connected with one of the source and drain electrodes through the second via hole; and

the gate electrode is on the gate insulating layer;

wherein the gate electrode is covered by a transparent conducting film, and the gate electrode is in direct contact with the transparent conducting film.

2. The method according to claim 1, wherein the forming source and drain electrodes on a substrate having a light shielding layer and a buffer layer covering the light shielding layer formed thereon, by a patterning process comprises:

forming the source and drain electrodes and a first via hole on the substrate having the light shielding layer and the buffer layer covering the light shielding layer formed thereon, by the patterning process.

3. The method according to claim 2, wherein the forming the source and drain electrodes and a first via hole on the substrate having the light shielding layer and the buffer layer covering the light shielding layer formed thereon, by the patterning process comprises:

forming the light shielding layer on the substrate;

depositing the buffer layer and a source/drain metal film sequentially on the substrate having the light shielding layer formed thereon; and

forming the source and drain electrodes and the first via hole that are located on the buffer layer by the patterning process using a halftone mask or a grey tone mask.

4. The method according to claim 3, wherein the forming the source and drain electrodes and the first via hole that are located on the buffer layer by the patterning process using a halftone mask or a grey tone mask, comprises:

coating a layer of photoresist on the source/drain metal film;

exposing and developing the photoresist in a stepwise manner by using the halftone mask plate or the grey tone mask plate, to form a completely-exposed area at a position of the first via hole, a non-exposed area at a position of the source and drain electrodes, and a partially-exposed area at other positions;

forming the first via hole by etching the source/drain metal film and the buffer layer in the completely-exposed area sequentially; and

subsequent to an ashing process, etching the source/drain metal film in the partially-exposed area, peeling the photoresist and forming the source and drain electrodes.

5. The method according to claim 2, wherein after depositing the active layer film and the gate insulating layer film sequentially and before forming the active layer, the gate insulating layer and the second via hole by the patterning process, the method further comprises:

forming a color resist layer on the gate insulating layer film; and

forming a planarization layer on the color resist layer.

6. The method according to claim 2, wherein the forming an active layer, a gate insulating layer and a second via hole by a patterning process comprises:

coating a layer of photoresist, and exposing and developing the photoresist in a stepwise manner by using a halftone mask plate or a grey tone mask plate, to form a non-exposed area at a position of the gate insulating layer, a partially-exposed area at a position of the active layer, and a completely-exposed area at a position of the second via hole and other positions;

etching the gate insulating layer film and the active layer film in the completely-exposed area sequentially, and forming the second via hole;

subsequent to an ashing process, etching the gate insulating layer film in the partially-exposed area, and forming the active layer; and

peeling the photoresist in the non-exposed area and forming the gate insulating layer.

7. The method according to claim 6, wherein after the etching the gate insulating layer film in the partially-exposed area, the method further comprises:

performing a conducting process on the active layer.

8. The method according to claim 6, wherein after depositing the active layer film and the gate insulating layer film sequentially and before coating the layer of photoresist, and exposing and developing the photoresist in the stepwise manner by using the halftone mask plate or the grey tone mask plate, the method further comprises:

forming a color resist layer on the gate insulating layer film; and

forming a planarization layer on the color resist layer;

wherein during a process of coating the layer of photoresist, and exposing and developing the photoresist in the stepwise manner by using the halftone mask plate or the grey tone mask plate, a non-exposed area is formed at a position of the planarization layer.

9. The method according to claim 2, further comprising:

forming a pixel definition layer, wherein the pixel definition layer is configured to expose the light emitting area.

10. The method according to claim 2, wherein the oxide active layer is made of indium gallium zinc oxide or indium tin zinc oxide;

the source and drain electrodes comprise three layers stacked sequentially, among which, the first and third layers comprise a Mo—

Nb alloy, and the second layer comprises copper the gate insulating layer film comprises a composite film made of SiNx, SiOx or SiNx/SiOx; and

the buffer layer comprises a composite film made of SiNx, SiOx or SiNx/SiOx.

11. The method according to claim 1, wherein a size of the gate electrode is less than that of the gate insulating layer, and a projection area of the gate electrode on the substrate is located within a projection area of the gate insulating layer on the substrate.

12. An AMOLED back plate, comprising:

a substrate;

a light shielding layer arranged on the substrate;

a buffer layer covering the light shielding layer;

source and drain electrodes arranged on the buffer layer;

an active layer, wherein the active layer covers at least a part of a surface of the source and drain electrodes, the surface being at a side of the source and drain electrodes which is farther away from the substrate;

a gate insulating layer arranged on the active layer;

a gate electrode arranged on the gate insulating layer; and

a transparent anode, wherein the transparent anode is arranged in a light emitting area and connected with one of the source and drain electrodes through a second via hole;

wherein the gate electrode is covered by a transparent conducting film, and the gate electrode is in direct contact with the transparent conducting film.

13. The back plate according to claim 12, wherein the oxide active layer is made of indium gallium zinc oxide or indium tin zinc oxide;

and the source and drain electrodes comprise three layers stacked sequentially, among which, the first and third layers comprise a Mo—

Nb alloy, and the second layer comprises copper.

14. The back plate according to claim 12, further comprising:

a color resist layer arranged on the gate insulating layer;

a planarization layer arranged on the color resist layer; and

a pixel definition layer arranged on the gate electrode and the transparent anode, configured to expose the light emitting area.

15. A display panel, comprising the AMOLED back plate according to claim 12.

16. A display device, comprising the display panel according to claim 15.

17. The back plate according to claim 12, wherein the active layer comprises a conductive part, and the conductive part is connected with the light shielding layer through a first via hole.

18. The back plate according to claim 12, wherein an upper surface and a side surface of the gate electrode are covered by the transparent conducting film and are in direct contact with the transparent conducting film.