Multi-phase current mode control loop incorporating a distributed transconductance stage

• US 10,520,970 B2
• Filed: 09/30/2015
• Issued: 12/31/2019
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Fletcher, Jay B., Searles, Shawn, Gozzini, Fabio, Pant, Sanjay
• Primary Examiner(s): Ahmed, Yusef A
• Assistant Examiner(s): Ahmad, Shahzeb K
• Application Number:
  US14/870,661
• Publication Number:
  US 20170090501A1
• Time in Patent Office: 1,553 Days
• CPC Class Codes: G05F 3/08 wherein the variable is dc
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved

Abstract

A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to a common output node. Each of the phase units may be configured to source current to the output node in response to the assertion of a respective clock signal in order to generate a regulated supply voltage. Each phase unit includes a respective transconductance amplifier configured to generate a respective demand current dependent upon a reference voltage and the regulated supply voltage.

Claims

1. An apparatus, comprising:

a first phase unit including a first transconductance amplifier and a first inductor coupled to a regulated supply voltage node, wherein the first phase unit is configured to;

source, via the first inductor, a first current to the regulated supply voltage node using a common power supply signal, wherein the first current is sourced in response to setting a first latch using a first pulse signal generated using a first clock signal;

generate, using the first transconductance amplifier, a first demand current using a reference voltage and a voltage level of the regulated supply voltage node; and

halt sourcing the first current using a first result of a first comparison between a compensated version of the first current and the first demand current; and

a second phase unit including a second transconductance amplifier and a second inductor coupled to the regulated supply voltage node, wherein the second phase unit is configured to;

source, via the second inductor, a second current to the regulated supply voltage node using the common power supply signal, wherein the second current is sourced in response to setting a second latch using a second pulse signal generated using a second clock signal;

generate, using the second transconductance amplifier and independent of the first demand current, a second demand current using the reference voltage and the voltage level of the regulated supply voltage node; and

halt sourcing of the second current using a second result of a second comparison between a compensated version of the second current and the second demand current;

wherein the first demand current used in the first comparison to halt sourcing of the first current does not have a contribution from the second demand current; and

wherein the second demand current used in the second comparison to halt sourcing of the second current does not have a contribution from the first demand current.

2. The apparatus of claim 1, wherein the first phase unit includes a first driver circuit including at least one n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and at least one p-channel MOSFET, wherein to source the first current to the first inductor, the first phase unit is further configured to activate the at least one p-channel MOSFET, and wherein the first phase unit is further configured to activate the at least one n-channel metal-oxide semiconductor field-effect transistor using the first result.

3. The apparatus of claim 1, wherein a phase of the first clock signal is different than a phase of the second clock signal.

4. The apparatus of claim 1, further comprising a reference generator unit configured to generate the reference voltage.

5. The apparatus of claim 1, further comprising a clock generator unit configured to generate the first clock signal and the second clock signal using a system clock signal.

6. A method for operating a voltage regulator unit, the method comprising:

initiating a first charge cycle of a first phase unit of a plurality of phase units in response to setting a first latch using a first pulse signal generated using a first clock signal of a plurality of clock signals;

initiating a second charge cycle of a second phase unit of the plurality of phase units in response to setting a second latch using a second pulse signal generated using a second clock signal of the plurality of clock signals;

sourcing, via a first inductor and using a common power supply signal, a first current to a load circuit by the first phase unit during the first charge cycle of the first phase unit;

sourcing, via a second inductor and using the common power supply signal, a second current to the load circuit by the second phase unit during the second charge cycle of the second phase unit;

halting the first charge cycle of the first phase unit using a first result of a first comparison between a first demand current and a compensated version of the first current, wherein the first demand current is generated using a voltage level at an output of the voltage regulation unit and a reference voltage level; and

halting the second charge cycle of the second phase unit using a second result of a second comparison between a second demand current and a compensated version of the second current, wherein the second demand current is generated using the voltage level at the output of the voltage regulation unit and the reference voltage level;

wherein the first demand current used in the first comparison to halt sourcing of the first current does not have a contribution from the second demand current; and

wherein the second demand current used in the second comparison to halt sourcing of the second current does not have a contribution from the first demand current.

7. The method of claim 6, wherein an assertion of the second clock signal occurs after a predetermined period of time has elapsed since an assertion of the first clock signal.

8. The method of claim 6, wherein a value of the first demand current is proportional to a difference between the voltage level at the output of the voltage regulator unit and the reference voltage level.

9. The method of claim 6, wherein halting the first charge cycle includes resetting the first latch using the first result.

10. The method of claim 6, wherein the plurality of phase units is included in a common integrated circuit package.

11. An apparatus, comprising:

a first phase unit including a first inductor that is coupled to a regulated supply signal, wherein the first phase unit is configured to;

source, in response to setting a first latch and using a common input power supply, a first current to the regulated supply signal via the first inductor, wherein the first latch is set using a first pulse signal generated using a first clock signal; and

halt sourcing the first current based on a first comparison of a compensated version of the first current and a first demand current, wherein the first demand current is generated using a voltage level of the regulated supply signal and a reference voltage level; and

a second phase unit including a second inductor that is coupled to the regulated supply signal, wherein the second phase unit is configured to;

source, in response to setting a second latch and using the common input power supply, a second current to the regulator supply signal via the second inductor, wherein the second latch is set using a second pulse signal generated using a second clock signal; and

halt sourcing the second current based on a second comparison of a compensated version of the second current and a second demand current, wherein the second demand current is generated using the voltage level of the regulated supply signal and the reference voltage level;

wherein the first demand current used in the first comparison to halt sourcing of the first current does not have a contribution from the second demand current; and

wherein the second demand current used in the second comparison to halt sourcing of the second current does not have a contribution from the first demand current.

12. The apparatus of claim 11, wherein to source the first current, the first phase unit is further configured to enable a transistor coupled between the common input power supply and the first inductor.

13. The apparatus of claim 11, wherein each of the first and second phase units are included in a common integrated circuit package.

14. The apparatus of claim 11, wherein each of the first and second phase units are included on a single integrated circuit.

15. The apparatus of claim 11, further comprising a reference generator configured to generate the reference voltage level.

16. The apparatus of claim 11, wherein the second clock signal lags the first clock signal.

17. The apparatus of claim 11, further comprising a clock generator unit configured to generate the first and second clock signals.