Non-binary rank multiplication of memory module
First Claim
Patent Images
1. A system, comprising:
- a memory controller;
a processor;
a non-transitory computer readable medium including instructions executable by the processor to repurpose a chip select input of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) to an address input, and reroute the address input of the repurposed chip select input to a plurality of memory ranks of the LRDIMM to support non-binary rank multiplication of the LRDIMM, wherein the LRDIMM is to present a number of logical ranks to the memory controller, and the non-binary rank multiplication comprises the non-binary rank multiplication of the number of logical ranks to provide the plurality of memory ranks of the LRDIMM; and
a buffer to map a selected logical rank of the number of logical ranks as selected by the memory controller using the plurality of chip select inputs, to a selected memory rank of the plurality of memory ranks, the selected memory rank selected based on selection using an address provided by the memory controller and a remainder of the plurality of chip select inputs other than the repurposed chip select input, wherein the buffer is to be set to a binary rank multiplication number greater than a non-binary rank multiplication supported by the LRDIMM and larger than a number of the plurality of memory ranks of the LRDIMM, wherein the non-binary rank multiplication is associated with a non-binary rank number of the plurality of memory ranks.
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Abstract
One of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) may be repurposed to an address input. One of a plurality of memory ranks of the LRDIMM may be selected based on a remainder of the plurality of chip select inputs. The repurposed chip select input may be used to support non-binary rank multiplication of the LRDIMM.
7 Citations
19 Claims
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1. A system, comprising:
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a memory controller; a processor; a non-transitory computer readable medium including instructions executable by the processor to repurpose a chip select input of a plurality of chip select inputs of a load-reduced dual inline memory module (LRDIMM) to an address input, and reroute the address input of the repurposed chip select input to a plurality of memory ranks of the LRDIMM to support non-binary rank multiplication of the LRDIMM, wherein the LRDIMM is to present a number of logical ranks to the memory controller, and the non-binary rank multiplication comprises the non-binary rank multiplication of the number of logical ranks to provide the plurality of memory ranks of the LRDIMM; and a buffer to map a selected logical rank of the number of logical ranks as selected by the memory controller using the plurality of chip select inputs, to a selected memory rank of the plurality of memory ranks, the selected memory rank selected based on selection using an address provided by the memory controller and a remainder of the plurality of chip select inputs other than the repurposed chip select input, wherein the buffer is to be set to a binary rank multiplication number greater than a non-binary rank multiplication supported by the LRDIMM and larger than a number of the plurality of memory ranks of the LRDIMM, wherein the non-binary rank multiplication is associated with a non-binary rank number of the plurality of memory ranks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 17)
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8. A method, comprising:
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receiving, at a load-reduced dual inline memory module (LRDIMM), a plurality of chip select inputs from a memory controller, wherein the LRDIMM is to present a number of logical ranks to the memory controller; repurposing, at the LRDIMM, a chip select input of the plurality of chip select inputs to be an address input of an address range, wherein the address input of the repurposed chip select input is rerouted to a plurality of memory ranks of the LRDIMM, the repurposed chip select input supporting non-binary rank multiplication of the LRDIMM, and the non-binary rank multiplication comprises the non-binary rank multiplication of the number of logical ranks to produce a quantity of the plurality of memory ranks of the LRDIMM; and selecting a selected memory rank of the plurality of memory ranks based on a remainder of the chip select inputs other than the repurposed chip select input, the selecting comprising mapping, using a buffer, a selected logical rank of the number of logical ranks as selected by the memory controller using the plurality of chip select inputs, to the selected memory rank of the plurality of memory ranks, wherein the buffer is set to a binary rank multiplication number greater than the non-binary rank multiplication supported by the LRDIMM and larger than the quantity of the plurality of memory ranks of the LRDIMM, wherein the non-binary rank multiplication is associated with a non-binary rank number of the plurality of memory ranks. - View Dependent Claims (9, 10, 11, 12, 18, 19)
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13. A system comprising:
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a memory controller; and a load-reduced dual inline memory module (LRDIMM) comprising a processor to; repurpose a chip select input of a plurality of chip select inputs to be an address input of a plurality of address inputs at the LRDIMM, wherein the LRDIMM is to present a number of logical ranks to the memory controller, the repurposed chip select input supporting non-binary rank multiplication of the LRDIMM, and the non-binary rank multiplication comprises the non-binary rank multiplication of the number of logical ranks to produce a quantity of a plurality of memory ranks of the LRDIMM; and select a selected memory rank of the plurality of memory ranks of the LRDIMM based on the plurality of chip select inputs, the LRDIMM comprising a buffer to map a selected logical rank of the number of logical ranks as selected by the memory controller using the plurality of chip select inputs, to the selected memory rank of the plurality of memory ranks, wherein the buffer is set to a binary rank multiplication number of a buffer to be greater than the non-binary rank multiplication supported by the LRDIMM and larger than the quantity of the plurality of memory ranks of the LRDIMM, wherein the non-binary rank multiplication is associated with a non-binary rank number of the plurality of memory ranks. - View Dependent Claims (14, 15, 16)
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Specification