Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation

• US 10,522,237 B2
• Filed: 10/07/2016
• Issued: 12/31/2019
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Pillay, Sanjay
• Primary Examiner(s): Lin, Sun J
• Application Number:
  US15/288,912
• Publication Number:
  US 20170212972A1
• Time in Patent Office: 1,180 Days
• Field of Search: 716106, 716109, 716133
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 2117/02 Fault tolerance, e.g. for transient fault suppression
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/22 Accessing serial memories
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/54 Arrangements for designing test circuits, e.g. design for test [DFT] tools
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Abstract

Low power very large scale integrated (VLSI) designs using a circuit failure in sequential cells as low voltage check for limit of operation of a design are provided. One such method involves the adding a plurality of bits for sequential elements in the design including sets of flip-flops, RAMs, ROMs and register files to add parity or single error correct and double error detect mechanism, a method to detect the parity errors or a single bit error and a double bit error in the sequential elements, starting at a voltage of operation at a nominal value and gradually lowering voltage setting till a first error is detected in the sequential elements, increasing the voltage of operation by predetermined step above a voltage of first fail to achieve an optimal voltage setting of a correct operation of the design, storing this optimal voltage setting in anon-volatile memory for a subsequent use.

Claims

1. A method comprising:

providing a design for a digital electronic device;

creating a circuit wrapper around sequential elements in the design, wherein said circuit wrapper adds a plurality of bits to each sequential element of the sequential elements;

determining a lowest voltage V_min at which the design will operate correctly by operating the design at successively lower voltages until a point at which a failure is reached; and

operating the design at the V_min.

2. The method of claim 1, further comprising:

detecting a correct operation of said each sequential element by utilizing a circuit to read the plurality of bits added to said each sequential element.

3. The method of claim 2, wherein a first voltage at which a point of a failure is reached by operating the design at successively lower voltages is V_fail, and wherein the V_min is obtained by adding a predetermined margin to the V_fail.

4. The method of claim 1, wherein a first voltage at which a point of a failure is reached is V_fail, and further comprising:

storing the V_min in a non-volatile memory.

5. The method of claim 4, further comprising:

restoring the voltage to a value of the V_min stored in the non-volatile memory.

6. The method of claim 1, further comprising:

generating a parity bit for each input bit of a plurality of input bits of the sequential elements in the design through the use of the circuit wrapper, wherein each sequential element of the sequential elements is selected from a group consisting of flip-flops, RAMs, ROMs and register files, and wherein each bit of the parity bits has a value of either an even or an odd parity.

7. The method of claim 6, further comprising:

checking an output of each sequential element of the sequential elements in the design for a correctness based on an associated parity bit.

8. The method of claim 7, wherein the determining V_min includes:

iteratively lowering the voltage based on the correctness of the output of each sequential element of the sequential elements.

9. The method of claim 8, further comprising:

increasing the voltage by a predetermined step once the failure is detected based on the correctness of the output of each sequential element of the sequential elements.

10. The method of claim 1, further comprising:

generating single error correct and double error detect (SECDED) code words for sequential elements in the design, wherein each sequential element of said sequential elements is selected from a group consisting of flip-flops, RAMs, ROMs and register files.

11. The method of claim 10, further comprising:

checking an output of each sequential element in the design for a correctness based on an associated SECDED code word.

12. The method of claim 11, wherein the determining V_min includes:

iteratively lowering the voltage based on the correctness of the output of each sequential element of the sequential elements.

13. The method of claim 12, further comprising:

increasing the voltage by a predetermined step once the failure is detected based on the correctness of the output of each sequential element of the sequential elements.

14. The method of claim 1, wherein the digital electronic device is a very large scale integrated (VLSI) design.

15. A method for detecting errors in a plurality of flip-flops in a very large scale integrated (VLSI) design, the method comprising:

grouping the plurality of flip-flops into sets of flip-flops; and

for each set of flip-flops,

(a) XORing inputs of member flip-flops of said each set to create a first signal,

(b) XORing outputs of said member flip-flops of said each set to create a second signal,

(c) inputting the first signal into a parity flip-flop associated with said each set of flip-flops to generate an output signal,

(d) comparing the output signal of the parity flip-flop and the second signal, and

(e) outputting an error signal if the output signal of the parity flip-flop and the second signal do not match.

16. A method for detecting errors in a plurality of flip-flops in a very large scale integrated (VLSI) design containing flip-flops, 1-bit memory devices and 2-bit memory devices, the method comprising:

receiving a first set, a second set and a third set of error signals corresponding to the flip-flops, the 1-bit memory devices and the 2-bit memory devices, respectively;

ORing the first set of error signals to generate a first check signal;

ORing the second set of error signals to generate a second check signal;

ORing the third set of error signals to generate a third check signal;

inputting the first check signal, the second check signal and the third check signal into a first parity flip-flop, a second parity flip-flop and a third parity flip-flop, respectively;

comparing an output signal of the first parity flip-flop to the first check signal, and generating an error code indicating an error in the flip-flops if the output signal and the first check signal do not match;

comparing an output signal of the second parity flip-flop to the second check signal, and generating an error code indicating an error in the 1-bit memory devices if an output signal and the second check signal do not match; and

comparing the output signal of the third parity flip-flop to the third check signal, and generating an error code indicating an error in the 2-bit memory devices if the output signal and the third check signal do not match.