Mixed style bias network for RF switch FET stacks

  • US 10,523,195 B1
  • Filed: 08/02/2018
  • Issued: 12/31/2019
  • Est. Priority Date: 08/02/2018
  • Status: Active Grant
First Claim
Patent Images

1. A FET switch stack, including:

  • (a) a first sub-stack including;

    (1) one or more series-connected ACS FETs, each ACS FET having a gate terminal; and

    (2) a rung gate resistor bias network comprising gate resistors each coupled to a first control voltage and to the gate terminal of a corresponding one of the ACS FETs of the first sub-stack;

    (b) a second sub-stack, series connected to the first sub-stack, including;

    (1) two or more series-connected ACS FETs, each ACS FET having a gate terminal; and

    (2) a rail gate resistor bias network comprising series gate resistors each coupled, directly or indirectly, to a second control voltage and to the respective gate terminals of at least two of the ACS FETs of the second sub-stack.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×