Tile for an active electronically scanned array (AESA)

• US 10,541,461 B2
• Filed: 12/16/2016
• Issued: 01/21/2020
• Est. Priority Date: 12/16/2016
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Teshiba, Mary A., Milne, Jason G., Rolston, Kevin C., Drab, John J.
• Primary Examiner(s): Magallanes, Ricardo I
• Application Number:
  US15/381,286
• Publication Number:
  US 20180175476A1
• Time in Patent Office: 1,131 Days
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6672 for integrated passive components, e.g. semiconductor device with passive components only integrated circuits with passive components only per se H01L27/01
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04 Structure, shape, material or disposition of the bonding areas prior to the connecting process
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05576 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73251 : on different surfaces
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80902 : by means of a further bonding area
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01Q 1/02 : Arrangements for de-icing; Arrangements for drying-out ; Arrangements for cooling; Arrangements for preventing corrosion
• CPC Class Codes: H01Q 1/526 : Electromagnetic shields
• CPC Class Codes: H01Q 21/0025 : Modular arrays
• CPC Class Codes: H01Q 21/0075 : Stripline fed arrays H01Q21/065 takes precedence
• CPC Class Codes: H01Q 21/061 : Two dimensional planar arrays
• CPC Class Codes: H01Q 23/00 : Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 3/36 : with variable phase-shifters

Abstract

In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

Claims

1. An active electronically scanned array (AESA) tile comprising:

a radiator structure; and

oxide-bonded semiconductor wafers attached to the radiator structure and comprising a low loss glass radio frequency (RF) manifold and a beam former, wherein the RF manifold is not in direct contact with the beam former;

wherein an RF signal path through the oxide-bonded semiconductor wafers comprises a first portion that propagates toward the beam former, a second portion that propagates parallel to the beam former, a third portion that propagates away from the beam former, and a fourth portion that extends into the beam former and out of the beam former;

wherein the RF signal path moves along three axes,

wherein the first portion, the third portion and the fourth portion of the RF signal move in a Z-axis direction,

wherein the second portion of the RF signal moves in an X-axis direction, and

a fifth portion of the RF signal moves in a Y-axis direction.

2. The AESA tile of claim 1, wherein the oxide-bonded semiconductor wafers are fused silica.

3. The AESA tile of claim 1, wherein the oxide-bonded semiconductor wafers comprise metal posts, and

wherein a metal post from one wafer is connected to a metal post of another wafer.

4. The AESA tile of claim 1, wherein the beam former comprises at least one of a phase shifter, an amplifier or an application-specific integrated circuit (ASIC).

5. The AESA tile of claim 1, wherein the beam former is fabricated on silicon germanium (SiGe) wafer.

6. The AESA tile of claim 1, wherein the radiator structure provides radiation shielding for the beam former.

7. The AESA tile of claim 1, wherein the RF manifold propagates RF signals and no DC signals.

8. The AESA tile of claim 1, wherein the beam former includes a redistribution layer to allow for surface mounting to a printed circuit board.

9. The AESA tile of claim 1, wherein power, signal and RF are routed from the PWB through the beam former by a wafer via.

10. The AESA tile of claim 1, where the oxide-bonded semiconductor wafers are made of high resistivity silicon.

11. The AESA tile of claim 1 where the RF signal is routed using at least one of a stripline, a coplanar waveguide (CPW), a buried microstrip and a coaxial RF structure.

12. The AESA tile of claim 1, wherein the tile comprises time delay structures and filtering structures.

13. The AESA tile of claim 1, further comprising active elements,

wherein active element spacing fits within Lambda/2 to enable wide scan to 60 degrees.

14. The AESA tile of claim 13, wherein the number of active elements between sixteen to sixty-four active elements.

15. The AESA tile of claim 13, wherein the tiles are scalable to an N×

N array of active elements where N>

1.

16. The AESA tile of claim 1 further comprising one or more time delay structures having a trace length selected to achieve a certain time delay.

17. The AESA tile of claim 1 further comprising a cooling plate that is positioned to cool the beamformer.

18. The AESA tile of claim 1 wherein the oxide-bonded semiconductor wafers are a stack of oxide-bonded wafers that are interconnected using RF direct bond hybridization (RF-DBH) and wafer vias.

19. The AESA tile of claim 1 wherein the fifth portion of the RF signal moves in the Y-axis direction in the RF manifold.