Intelligent high bandwidth memory appliance
First Claim
1. An HBM+ system, comprising:
- a host including at least one of a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA); and
an HBM+ stack including a plurality of high bandwidth memory (HBM) modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules;
wherein the logic die comprises;
an HBM controller including a memory controller configured to interface with the plurality of HBM modules; and
an offload processing logic section configured to offload processing operations from the host, andwherein;
the offload processing logic section is configured to receive a first flag set by the host to indicate that the offload processing operations should begin;
the offload processing logic section is configured to perform the offload processing operations using the HBM controller responsive to the first flag; and
the HBM controller is configured to set a second flag to indicate that the offload processing operations are complete.
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Accused Products
Abstract
Inventive aspects include An HBM+ system, comprising a host including at least one of a CPU, a GPU, an ASIC, or an FPGA; and an HBM+ stack including a plurality of HBM modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules. The logic die is configured to offload processing operations from the host. A system architecture is disclosed that provides specific compute capabilities in the logic die of high bandwidth memory along with the supporting hardware and software architectures, logic die microarchitecture, and memory interface signaling options. Various new methods are provided for using in-memory processing abilities of the logic die beneath an HBM memory stack. In addition, various new signaling protocols are disclosed to use an HBM interface. The logic die microarchitecture and supporting system framework are also described.
13 Citations
23 Claims
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1. An HBM+ system, comprising:
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a host including at least one of a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA); and an HBM+ stack including a plurality of high bandwidth memory (HBM) modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules; wherein the logic die comprises; an HBM controller including a memory controller configured to interface with the plurality of HBM modules; and an offload processing logic section configured to offload processing operations from the host, and wherein; the offload processing logic section is configured to receive a first flag set by the host to indicate that the offload processing operations should begin; the offload processing logic section is configured to perform the offload processing operations using the HBM controller responsive to the first flag; and the HBM controller is configured to set a second flag to indicate that the offload processing operations are complete. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A logic die, comprising:
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a host manager including an interface PHY and a host queue manager, wherein the host manager is configured to interface with a host via the interface PHY, and to queue communications received from the host; a memory controller including a prefetch engine and a cache controller, wherein the memory controller is configured to interface with a memory via the prefetch engine and the cache controller; a High Bandwidth Memory (HBM) controller including a memory controller configured to interface with a stack of HBM modules; and an offload processing logic section configured to offload processing operations from the host, wherein; the received information includes a first flag set by the host to indicate processing should begin; the offload processing logic section is configured to perform the processing operations using the HBM controller responsive to the first flag; and the HBM controller is configured to set a second flag to indicate that the processing operations are complete. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification