Semiconductor memory device and method of manufacturing the same

• US 10,546,871 B2
• Filed: 09/12/2016
• Issued: 01/28/2020
• Est. Priority Date: 03/23/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Aoyama, Kenji
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Isaac, Stanetta D
• Application Number:
  US15/262,340
• Publication Number:
  US 20170278860A1
• Time in Patent Office: 1,233 Days
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A semiconductor memory device according to an embodiment comprises: a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate; a stepped part for contacting the plurality of conductive layers to a wiring line; a contact extending in the first direction and being connected to the conductive layer in the stepped part; and a plurality of columnar bodies extending in the first direction and penetrates the conductive layer in the stepped part and including a first columnar body having a first height and a second columnar body having a second height which is lower than the first height.

Claims

1. A semiconductor memory device, comprising:

a memory cell array region including a plurality of conductive layers that are electrically connected to a plurality of memory cells arranged in a first direction on a semiconductor substrate, the first direction intersecting a surface of the semiconductor substrate;

a stepped part for contacting the plurality of conductive layers to a wiring line;

a contact extending in the first direction and being connected to the conductive layer in the stepped part; and

a plurality of columnar bodies extending in the first direction, each columnar body including a support column extending in the first direction, and each columnar body penetrating through the conductive layer in the stepped part, the plurality of columnar bodies including a first columnar body having an upper end on an opposite side to the substrate at a first height from the surface of the semiconductor substrate and a second columnar body having an upper end on an opposite side to the substrate at a second height from the surface of the semiconductor substrate, the second height being lower than the first height.

2. The semiconductor memory device according to claim 1, wherein

the stepped part up to the second height has the second columnar body provided therein, and the stepped part above the second height has the first columnar body provided therein.

3. The semiconductor memory device according to claim 1, wherein

the second height is not less than half of the first height.

4. The semiconductor memory device according to claim 1, wherein

the stepped part is disposed on each of both sides sandwiching the memory cell array region.

5. The semiconductor memory device according to claim 1, wherein

the columnar body is composed of materials including oxygen and silicon.

6. The semiconductor memory device according to claim 1, wherein

the first columnar body and the second columnar body are composed of different materials.

7. The semiconductor memory device according to claim 1, wherein

each of the plurality of memory cells includes a semiconductor layer extending in the first direction and a memory film provided on a side surface of the semiconductor layer, and

the first columnar body includes the semiconductor layer and the memory film.

8. The semiconductor memory device according to claim 1, wherein

a distance between extremities of the conductive layers adjacent in the first direction up to the conductive layer having the second height is shorter than that of the conductive layers adjacent in the first direction above the second height.

9. The semiconductor memory device according to claim 1, wherein

the plurality of conductive layers configuring the stepped part each include a projecting part whose end projects more than an end of the conductive layer adjacent upwardly in the first direction, and

the contact and the columnar body are provided in an identical one of the projecting parts.

10. The semiconductor memory device according to claim 9, wherein

a distance between the first columnar body and the contact provided in one of the projecting parts is shorter than a distance between the second columnar body and the contact provided in another one of the projecting parts.

11. The semiconductor memory device according to claim 1, wherein

the plurality of columnar bodies include a plurality of the first columnar bodies whose upper ends are located at the first height of same value from the surface of the substrate and a plurality of the second columnar bodies whose upper ends are located at the second height of same value from the surface of the substrate.

12. The semiconductor memory device according to claim 11, wherein

the plurality of conductive layers stacked to a height above the second height are arranged in a first region of the stepped part where the plurality of first columnar bodies are provided, and the plurality of conductive layers stacked up to the second height are arranged in a second region of the stepped part where the plurality of second columnar bodies are provided.