Systems, apparatuses and methods for dual line inbound detection on a data communication bus

• US 10,552,361 B2
• Filed: 11/28/2016
• Issued: 02/04/2020
• Est. Priority Date: 07/27/2016
• Status: Active Grant

• Current Assignee: Hubbell, Inc.
• Original Assignee: Hubbell, Inc.
• Inventors: Ilijic, Nik, Jones, Andrew Rhydian
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US16/320,419
• Publication Number:
  US 20190266120A1
• Time in Patent Office: 1,163 Days
• Field of Search: 710314
• CPC Class Codes: G05B 19/00 Programme-control systems
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

An input/output (I/O) and control system for long distance communications and industrial applications is provided having a two wire bus and bus protocol for communications between field devices and a channel generator for monitoring and control of the field devices. The channel generator produces an offset square wave on the bus, and sends a synchronization pulse of selected duration at the start of each bus scan cycle in a pulse train cycle to reset counters in the field devices before the bus scan cycle is repeated, to ensure field devices are synchronized, transmitters transmit on the correct channel, and receivers sample the pulse cycle at the correct time. High side and low side current detectors for respective ones of the two wires of the bus and an algorithm are provided to improve detection of valid inbound transmissions by the channel generator for increased noise immunity.

Claims

1. A method of determining if a device has sent a valid inbound transmission on a bus that interfaces a control unit to plural devices connected to the bus,

the bus being a two wire bus having a signal line and a common return line,

the control unit being configured to generate a pulse train comprising

a plurality of cycles for transmission on the bus, each of the cycles comprising a low voltage level portion for a designated period of time and a high voltage level portion for a designated period of time, and at least some of the cycles corresponding to respective channel windows assigned to respective ones of the plural devices as I/O channels, and

bus scan cycles that each comprise a selected number of the I/O channels, and a synchronization pulse, the synchronization pulse being configured to ensure that the plural devices transmit and receive on their corresponding I/O channels and that the control unit samples the pulse train at a correct channel window corresponding to a selected one of the plural devices, and

each of the plural devices being configured to indicate an inbound transmission to the control unit by pulling down the signal line to a designated low voltage level during the low voltage level portion of its corresponding cycle,

the method comprising:

operating a high side current detector to detect current on the signal line;

operating a low side current detector to detect current on the common return line;

designating a signal threshold;

designating at least part of the low voltage level portion in each of the I/O channels to be that channel'"'"'s inbound detection period;

determining an average for a designated number of samples of the current detected by the high side current detector during a channel'"'"'s inbound detection period;

determining an average for a designated number of samples of the current detected by the low side current detector during the channel'"'"'s inbound detection period; and

determining an inbound transmission to be valid if the average of the samples from the low side current detector and the average of the samples from the high side current detector are both greater than the signal threshold.

2. The method of claim 1, further determining a signal on the bus to not be a valid inbound transmission when outputs from either one of the low side current detector and the high side current detector fails to meet one of the high side signal threshold and the low side signal threshold.

3. The method of claim 1, further comprising disabling the low side current detector during the high voltage pulse in the I/O channels.

4. A method of determining if a device has sent a valid inbound transmission on a bus that interfaces a control unit to plural devices connected to the bus,

the bus being a two wire bus having a signal line and a common return line,

the control unit being configured to generate a pulse train comprising

a plurality of cycles for transmission on the bus, each of the cycles comprising a low voltage level portion for a designated period of time and a high voltage level portion for a designated period of time, and at least some of the cycles corresponding to respective channel windows assigned to respective ones of the plural devices as I/O channels, and

bus scan cycles that each comprise a selected number of the I/O channels, and a synchronization pulse, the synchronization pulse being configured to ensure that the plural devices transmit and receive on their corresponding I/O channels and that the control unit samples the pulse train at a correct channel window corresponding to a selected one of the plural devices, and

each of the plural devices being configured to indicate an inbound transmission to the control unit by pulling down the signal line to a designated low voltage level during the low voltage level portion of its corresponding cycle,

the method comprising:

operating a high side current detector to detect current on the signal line;

operating a low side current detector to detect current on the common return line;

designating a high side signal threshold and a low side signal threshold;

designating at least part of the low voltage level portion in each of the I/O channels to be that channel'"'"'s inbound detection period;

determining an average for a designated number of samples of the current detected by the high side current detector during a channel'"'"'s inbound detection period;

determining an average for a designated number of samples of the current detected by the low side current detector during the channel'"'"'s inbound detection period; and

determining an inbound transmission to be valid if one of averages comprising the average of the samples from the low side current detector and the average of the samples from the high side current detector is greater than the high side signal threshold and the other one of the averages is greater than the low side signal threshold.

5. The method of claim 4, further determining a signal on the bus to not be a valid inbound transmission when outputs from either one of the low side current detector and the high side current detector fails to meet one of the high side signal threshold and the low side signal threshold.

6. The method of claim 4, further comprising disabling the low side current detector during the high voltage pulse in the I/O channels.

7. The method of claim 4, wherein the pulse train is an offset square wave and the high voltage level pulse is between 12 VDC and 48 VDC and the low voltage level portion is between 2 VDC and 9 VDC.

8. The method of claim 4, wherein the pulse train is a periodic waveform comprising instantaneous transition between the high voltage level pulse and the low voltage level portion.

9. The method of claim 4, wherein pulse train has a configurable frequency.

10. The method of claim 4, wherein the bus scan cycles comprise dual scan bus cycles having alternating A and B scan cycles where each A scan cycle and each B scan cycle comprises the selected number of I/O channels and that synchronization pulse.

11. The method of claim 4, wherein the pulse train is an offset square wave with configurable frequency, and comprises a selected number of cycles that are assigned to a corresponding number of the I/O channels and that are generated by the control unit.

12. The method of claim 11, wherein the selected number of I/O channels is configured in the control unit.