Thin-film transistor structure and manufacturing method thereof, display panel and display device

• US 10,553,621 B2
• Filed: 03/13/2018
• Issued: 02/04/2020
• Est. Priority Date: 07/28/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Hu, Hehe, Yang, Wei, Lu, Xinhong, Wang, Ke, Wen, Yu
• Primary Examiner(s): Shook, Daniel P
• Application Number:
  US16/302,850
• Publication Number:
  US 20190267409A1
• Time in Patent Office: 693 Days
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

Embodiment of the present disclosure provide a thin-film transistor structure, a manufacturing method thereof, a display panel and a display device. The thin-film transistor structure includes: a base substrate; and a first thin-film transistor and a second thin-film transistor formed on the base substrate, wherein a first active layer of the first thin-film transistor is doped with hydrogen; a material of a second active layer of the second thin-film transistor is metal oxide; and a first isolation barrier surrounding the first thin-film transistor and/or a second isolation barrier surrounding the second thin-film transistor are disposed on the base substrate.

Claims

1. A thin-film transistor structure, comprising:

a base substrate; and

a first thin-film transistor and a second thin-film transistor, formed on the base substrate, wherein

a first active layer of the first thin-film transistor is doped with hydrogen;

a material of a second active layer of the second thin-film transistor is metal oxide; and

a first isolation barrier surrounding the first thin-film transistor and/or a second isolation barrier surrounding the second thin-film transistor are disposed on the base substrate.

2. The thin-film transistor structure according to claim 1, wherein a second gate insulating layer of the second thin-film transistor covers the first thin-film transistor;

a first through hole surrounding the second thin-film transistor is disposed in the second gate insulating layer; and

the second isolation barrier is filled into the first through hole.

3. The thin-film transistor structure according to claim 2, wherein the first thin-film transistor is a low temperature polysilicon thin-film transistor;

and the second thin-film transistor is a bottom-gate thin-film transistor.

4. The thin-film transistor structure according to claim 3, wherein the first thin-film transistor includes a connecting electrode disposed on the second gate insulating layer;

the connecting electrode is connected with a drain electrode of first source/drain electrodes in the first thin-film transistor through a first connecting hole in the second gate insulating layer;

or, the connecting electrode is connected with a source electrode of the first source/drain electrodes in the first thin-film transistor through a second connecting hole in the second gate insulating layer.

5. The thin-film transistor structure according to claim 1, wherein the second isolation barrier includes a first portion and a second portion;

the first portion is disposed on the base substrate and covers an edge and a side surface of a first insulating layer of the first thin-film transistor surrounding the second thin-film transistor; and

a second gate insulating layer of the second thin-film transistor covers the first thin-film transistor and the first portion;

a region of the second gate insulating layer corresponding to the first portion is provided with a second through hole surrounding the second thin-film transistor;

the second portion is filled into the second through hole; and

the second portion is in contact with the first portion.

6. The thin-film transistor structure according to claim 1, wherein the first isolation barrier includes a third portion and a fourth portion, in which

the third portion is disposed on the base substrate and covers an edge and a side surface of a first insulating layer of the first thin-film transistor, being disposed on the base substrate and formed in a region of the first thin-film transistor and surrounding the first thin-film transistor;

a second gate insulating layer of the second thin-film transistor covers the first thin-film transistor and the third portion;

a region of the second gate insulating layer corresponding to the third portion is provided with a third through hole surrounding the first thin-film transistor;

the fourth portion is filled into the third through hole; and

the fourth portion is in contact with the third portion.

7. The thin-film transistor structure according to claim 6, wherein the first insulating layer includes the first gate insulating layer of the first thin-film transistor and a first interlayer insulating layer covering the first gate electrode of the first thin-film transistor.

8. The thin-film transistor structure according to claim 7, wherein the third portion covering the edge and the side surface of the first insulating layer of the first thin-film transistor, being disposed on the base substrate and formed in a region of the first thin-film transistor and surrounding the first thin-film transistor, includes:

the third portion covering a side surface of the first gate insulating layer of the first thin-film transistor, being disposed on the base substrate and formed in the region of the first thin-film transistor and surrounding the first thin-film transistor, and the third portion covering an edge and a side surface of the first interlayer insulating layer of the first thin-film transistor, being disposed on the base substrate and formed in the region of the first thin-film transistor and surrounding the first thin-film transistor.

9. The thin-film transistor structure according to claim 1, wherein the first isolation barrier is an organic material isolation barrier, an inorganic material isolation barrier or a metal isolation barrier;

and

the second isolation barrier is an organic material isolation barrier, an inorganic material isolation barrier or a metal isolation barrier.

10. A display panel, comprising the thin-film transistor structure according to claim 1.

11. A display device, comprising the display panel according to claim 10.

12. A method for manufacturing the thin-film transistor structure according to claim 1, comprising:

forming a first thin-film transistor, a second thin-film transistor and a first isolation barrier and/or a second isolation barrier on a base substrate, in which a first active layer of the first thin-film transistor is doped with hydrogen;

a material of a second active layer of the second thin-film transistor is metal oxide;

the first isolation barrier surrounds the first thin-film transistor; and

the second isolation barrier surrounds the second thin-film transistor.

13. The method for manufacturing the thin-film transistor structure according to claim 12, wherein the first thin-film transistor is a low temperature polysilicon thin-film transistor;

and the second thin-film transistor is a bottom-gate thin-film transistor; and

the forming the first thin-film transistor, the second thin-film transistor and the second isolation barrier on the base substrate includes;

forming the first thin-film transistor on the base substrate; and

forming the second thin-film transistor and the second isolation barrier surrounding the second thin-film transistor on the base substrate.

14. The method for manufacturing the thin-film transistor structure according to claim 13, wherein

the forming the first thin-film transistor on the base substrate includes:

forming a first active layer of the first thin-film transistor;

forming a first gate insulating layer of the first thin-film transistor;

forming a first gate electrode of the first thin-film transistor;

forming a first interlayer insulating layer of the first thin-film transistor;

forming an exposed hole, a first connecting hole and a second connecting hole running through the first interlayer insulating layer and the first gate insulating layer, in which the exposed hole exposes a region on the base substrate in which the second thin-film transistor is disposed;

the first active layer is exposed by both the first connecting hole and the second connecting hole; and

forming first source/drain electrodes of the first thin-film transistor and a second gate electrode of the second thin-film transistor, in which the first source/drain electrodes include a first source electrode and a first drain electrode;

the first source electrode is connected with the first active layer through the first connecting hole;

the first drain electrode is connected with the first active layer through the second connecting hole;

the second gate electrode is disposed on the base substrate and in the exposed hole; and

the forming the second thin-film transistor and the second isolation barrier surrounding the second thin-film transistor on the base substrate includes;

forming a second gate insulating layer of the second thin-film transistor;

forming a second active layer of the second thin-film transistor;

forming a first through hole surrounding the second thin-film transistor and exposing the base substrate, a third connecting hole corresponding to the first source electrode of the first thin-film transistor, or a fourth connecting hole corresponding to the first drain electrode of the first thin-film transistor in the second gate insulating layer; and

forming second source/drain electrodes of the second thin-film transistor, the second isolation barrier filled into the first through hole, and a connecting electrode which is connected with the first source electrode through the third connecting hole or connected with the first drain electrode through the fourth connecting hole.

15. The method for manufacturing the thin-film transistor structure according to claim 12, wherein the first thin-film transistor is a low temperature polysilicon thin-film transistor;

and the second thin-film transistor is a bottom-gate thin-film transistor; and

the forming the first thin-film transistor, the second thin-film transistor and the second isolation barrier on the base substrate includes;

forming the first thin-film transistor and a first portion of the second isolation barrier on the base substrate, in which the first portion covers an edge and a side surface of the first insulating layer of the first thin-film transistor surrounding the second thin-film transistor; and

forming the second thin-film transistor and a second portion of the second isolation barrier on the base substrate, in which the second portion is disposed on the first portion, and the first portion and the second portion surround the second thin-film transistor together.

16. The method for manufacturing the thin-film transistor structure according to claim 15, wherein

the forming the first thin-film transistor and the first portion of the second isolation barrier on the base substrate includes:

forming a first active layer of the first thin-film transistor;

forming a first gate insulating layer of the first thin-film transistor;

forming a first gate electrode of the first thin-film transistor;

forming a first interlayer insulating layer of the first thin-film transistor;

forming an exposed hole, a first connecting hole and a second connecting hole running through the first interlayer insulating layer and the first gate insulating layer, in which the exposed hole exposes a region on the base substrate in which the second thin-film transistor is disposed, and the first active layer is exposed by both the first connecting hole and the second connecting hole; and

forming first source/drain electrodes of the first thin-film transistor, a second gate electrode of the second thin-film transistor and the first portion of the second isolation barrier, in which the first source/drain electrodes include a first source electrode and a first drain electrode;

the first source electrode is connected with the first active layer through the first connecting hole;

the first drain electrode is connected with the first active layer through the second connecting hole;

the first portion covers an edge and a wall of the exposed hole;

the second gate electrode is disposed on the base substrate and in the exposed hole; and

the forming the second thin-film transistor and the second portion of the second isolation barrier on the base substrate includes;

forming a second gate insulating layer of the second thin-film transistor;

forming a second active layer of the second thin-film transistor;

forming a second through hole surrounding the second thin-film transistor and corresponding to the first portion, a third connecting hole corresponding to the first source electrode of the first thin-film transistor, or a fourth connecting hole corresponding to the first drain electrode of the first thin-film transistor in the second gate insulating layer; and

forming second source/drain electrodes of the second thin-film transistor, the second portion being filled into the second through hole and being in contact with the first portion, and a connecting electrode which is connected with the first source electrode through the third connecting hole or connected with the first drain electrode through the fourth connecting hole.

17. The method for manufacturing the thin-film transistor structure according to claim 12, wherein the first thin-film transistor is a low temperature polysilicon thin-film transistor;

and the second thin-film transistor is a bottom-gate thin-film transistor; and

the forming the first thin-film transistor, the second thin-film transistor and the first isolation barrier on the base substrate includes;

forming the first thin-film transistor and a third portion of the first isolation barrier on the base substrate, in which the third portion covers an edge and a side surface of the first insulating layer of the first thin-film transistor surrounding the first thin-film transistor; and

forming the second thin-film transistor and a fourth portion of the first isolation barrier on the base substrate, in which the fourth portion is disposed on the third portion, and the third portion and the fourth portion surround the first thin-film transistor together.

18. The method for manufacturing the thin-film transistor structure according to claim 17, wherein

the forming the first thin-film transistor and the third portion of the isolation barrier on the base substrate includes:

forming a first active layer of the first thin-film transistor;

forming a first gate insulating layer of the first thin-film transistor;

forming a first gate electrode of the first thin-film transistor;

forming a first interlayer insulating layer of the first thin-film transistor;

removing a portion of the first gate insulating layer and the first interlayer insulating layer disposed outside a region of the base substrate in which the first thin-film transistor is disposed, and forming a first connecting hole and a second connecting hole running through the first interlayer insulating layer and the first gate insulating layer, in which side surfaces of the first gate insulating layer and the first interlayer insulating layer are disposed in the region of the base substrate in which the first thin-film transistor is disposed;

the first active layer is exposed by both the first connecting hole and the second connecting hole; and

forming first source/drain electrodes of the first thin-film transistor, the second gate electrode of the second thin-film transistor and the third portion of the first isolation barrier, in which the first source/drain electrodes include a first source electrode and a first drain electrode;

the first source electrode is connected with the first active layer through the first connecting hole;

the first drain electrode is connected with the first active layer through the second connecting hole;

the third portion covers an edge and the side surface of the first interlayer insulating layer and the side surface of the first gate insulating layer;

the second gate electrode is disposed on the base substrate; and

the forming the second thin-film transistor and the fourth portion of the first isolation barrier on the base substrate includes;

forming a second gate insulating layer of the second thin-film transistor;

forming a second active layer of the second thin-film transistor;

forming a third through hole surrounding the first thin-film transistor and corresponding to the third portion, a third connecting hole corresponding to the first source electrode of the first thin-film transistor, or a fourth connecting hole corresponding to the first drain electrode of the first thin-film transistor in the second gate insulating layer; and

forming second source/drain electrodes of the second thin-film transistor, the fourth portion being filled in the third through hole and being in contact with the third portion, and a connecting electrode which is connected with the first source electrode through the third connecting hole or connected with the first drain electrode through the fourth connecting hole.