Semiconductor device

• US 10,553,726 B2
• Filed: 08/08/2017
• Issued: 02/04/2020
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Tsubuku, Masashi, Noda, Kosei, Toyotaka, Kouhei, Watanabe, Kazunori, Harada, Hikaru
• Primary Examiner(s): Gupta, Raj R
• Application Number:
  US15/671,199
• Publication Number:
  US 20170358683A1
• Time in Patent Office: 910 Days
• Field of Search: None
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Claims

1. A semiconductor device comprising a memory element, the memory element comprising:

a transistor; and

a capacitor,

wherein the transistor comprises an oxide semiconductor layer, a gate insulating layer over the oxide semiconductor layer and a gate electrode over the gate insulating layer,

wherein the oxide semiconductor layer comprises indium, zinc and a metal element other than indium and zinc,

wherein one of a source electrode and a drain electrode of the transistor is electrically connected to a row decoder through a first wiring,

wherein the other of the source electrode and the drain electrode of the transistor is electrically connected to one of terminals of the capacitor,

wherein the gate electrode of the transistor is electrically connected to a column decoder through a second wiring,

wherein the other one of terminals of the capacitor is electrically connected to a third wiring,

wherein an off-state current of the transistor is 1×

10<sup>−

12</sup> A or lower at a drain voltage of 6V and a gate voltage of −

5V or −

10V, and

wherein a hydrogen concentration in a channel formation region of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

2. The semiconductor device according to claim 1, wherein a carrier concentration in the channel formation region of the oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is a crystalline oxide semiconductor layer.

4. The semiconductor device according to claim 3, wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM.

6. A semiconductor device comprising a memory element, the memory element comprising:

a transistor; and

a capacitor,

wherein the transistor comprises an oxide semiconductor layer,

wherein one of a source electrode and a drain electrode of the transistor is electrically connected to a row decoder through a first wiring,

wherein the other of the source electrode and the drain electrode of the transistor is electrically connected to one of terminals of the capacitor,

wherein a gate electrode of the transistor is electrically connected to a column decoder through a second wiring,

wherein the other one of terminals of the capacitor is electrically connected to a third wiring, and

wherein an off-state current of the transistor is 1×

10<sup>−

12</sup> A or lower at a drain voltage of 6V and a gate voltage of −

5V or −

10V.

7. The semiconductor device according to claim 6, wherein a hydrogen concentration in a channel formation region of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

8. The semiconductor device according to claim 6, wherein a carrier concentration in a channel formation region of the oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

9. The semiconductor device according to claim 6, wherein the semiconductor device is a DRAM.

10. A semiconductor device comprising a memory element, the memory element comprising:

a transistor; and

a capacitor,

wherein the transistor comprises an oxide semiconductor layer,

wherein one of a source electrode and a drain electrode of the transistor is electrically connected to a row decoder through a first wiring,

wherein the other of the source electrode and the drain electrode of the transistor is electrically connected to one of terminals of the capacitor,

wherein a gate electrode of the transistor is electrically connected to a column decoder through a second wiring,

wherein the other one of terminals of the capacitor is electrically connected to a third wiring,

wherein an off-state current of the transistor is 1×

10<sup>−

12</sup> A or lower at a drain voltage of 6V and a gate voltage of −

5V or −

10V, and

wherein the oxide semiconductor layer is a crystalline oxide semiconductor layer.

11. The semiconductor device according to claim 10, wherein a hydrogen concentration in a channel formation region of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

12. The semiconductor device according to claim 10, wherein a carrier concentration in a channel formation region of the oxide semiconductor layer is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

13. The semiconductor device according to claim 10, wherein the semiconductor device is a DRAM.