Data storage device encoding and interleaving codewords to improve trellis sequence detection

• US 10,554,225 B2
• Filed: 08/20/2018
• Issued: 02/04/2020
• Est. Priority Date: 11/03/2015
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Chen, Yiming, Krishnan, Anantha Raman
• Primary Examiner(s): McMahon, Daniel F.
• Application Number:
  US16/105,689
• Publication Number:
  US 20190081642A1
• Time in Patent Office: 533 Days
• Field of Search: None
• CPC Class Codes: G11B 2020/1863 wherein the Viterbi algorithm is used for decoding the error correcting code
• CPC Class Codes: G11B 5/59616 Synchronisation; Clocking G11B5/59622 takes precedence
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/2742 Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
• CPC Class Codes: H03M 13/2757 Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/31 combining coding for error detection or correction and efficient use of the spectrum without error detection or correction H03M5/14 , H03M5/145
• CPC Class Codes: H03M 13/356 Unequal error protection [UEP]
• CPC Class Codes: H03M 13/4138 soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation
• CPC Class Codes: H03M 13/6513 Support of multiple code types, e.g. unified decoder for LDPC and turbo codes
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields

Abstract

A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.

Claims

1. A controller for use in a data storage device, comprising:

a communication interface configured to communicate data with a storage medium of a data storage device; and

a processor in data communication with the communication interface and configured to;

encode input data according to at least one channel code constraint to generate first data and second data;

encode the first data into a first codeword;

encode the second data into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword;

interleave the first codeword and the second codeword to generate an interleaved codeword; and

control the communication interface to write the interleaved codeword to the storage medium.

2. The controller as recited in claim 1, wherein the interleaved codeword comprises parity data not encoded according to the at least one channel code constraint.

3. The controller as recited in claim 1, wherein the at least one channel code constraint is a maximum transition run (MTR) constraint.

4. The controller as recited in claim 1, wherein the at least one channel code constraint is a run-length limit (RLL) constraint.

5. The controller as recited in claim 1, wherein the processor is configured to encode the first and second data using a low density parity check (LDPC) code.

6. The controller as recited in claim 1, wherein:

the channel code constraint limits at least one of a maximum transition run (MTR) length and a maximum run-length limit (RLL);

the interleaved codeword comprises an interleave segment length; and

the interleave segment length is less than or equal to the run-length of the channel code constraint.

7. Control circuitry for use in a data storage device, the control circuitry configured to:

encode input data according to at least one channel code constraint to generate first data and second data;

encode the first data into a first codeword;

encode the second data into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword;

interleave the first codeword and the second codeword to generate an interleaved codeword; and

write the interleaved codeword to a storage medium of a data storage device.

8. The control circuitry as recited in claim 7, wherein the interleaved codeword comprises parity data not encoded according to the at least one channel code constraint.

9. The control circuitry as recited in claim 7, wherein the at least one channel code constraint is a maximum transition run (MTR) constraint.

10. The control circuitry as recited in claim 7, wherein the at least one channel code constraint is a run-length limit (RLL) constraint.

11. The control circuitry as recited in claim 7, wherein the control circuitry is further configured to:

read the interleaved codeword from the storage medium to generate a read signal;

sample the read signal to generate signal samples;

process the signal samples with a trellis detector to generate a sequence of reliability metrics representing the interleaved codeword;

de-interleave the sequence of reliability metrics into a first set of reliability metrics representing the first codeword and a second set of reliability metrics representing the second codeword;

decode the first set of reliability metrics to generate a third set of reliability metrics representing the first codeword;

decode the second set of reliability metrics to generate a fourth set of reliability metrics representing the second codeword;

interleave the third set of reliability metrics and the fourth set of reliability metrics to generate interleaved reliability metrics representing the interleaved codeword; and

process the interleaved reliability metrics with the trellis detector.

12. The control circuitry as recited in claim 11, wherein the first code rate of the first codeword increases the accuracy of the trellis detector when processing the interleaved reliability metrics.

13. The control circuitry as recited in claim 11, wherein the trellis detector implements a soft-input soft-output Viterbi algorithm.

14. The control circuitry as recited in claim 11, wherein the control circuitry is further configured to:

decode the interleaved codeword based on the at least one channel code constraint.

15. The control circuitry as recited in claim 7, wherein the control circuitry is further configured to encode the first and second data using a low density parity check (LDPC) code.

16. The control circuitry as recited in claim 7, wherein:

the channel code constraint limits at least one of a maximum transition run (MTR) length and a maximum run-length limit (RLL);

the interleaved codeword comprises an interleave segment length; and

the interleave segment length is less than or equal to the run-length of the channel code constraint.

17. A data storage device comprising:

a storage medium; and

a controller configured to communicate data with the storage medium and configured to;

decode a first set of reliability metrics to generate a third set of reliability metrics representing a first codeword;

decode a second set of reliability metrics to generate a fourth set of reliability metrics representing a second codeword;

interleave the third set of reliability metrics and the fourth set of reliability metrics to generate interleaved reliability metrics representing the interleaved codeword; and

process the interleaved reliability metrics with a trellis detector.

18. The data storage device as recited in claim 17, wherein the controller is further configured to:

read the interleaved codeword from the storage medium to generate a read signal;

sample the read signal to generate signal samples;

process the signal samples with the trellis detector to generate a sequence of reliability metrics representing the interleaved codeword; and

de-interleave the sequence of reliability metrics into the first set of reliability metrics representing the first codeword and the second set of reliability metrics representing the second codeword.

19. The data storage device as recited in claim 17, wherein the first code rate of the first codeword increases the accuracy of the trellis detector when processing the interleaved reliability metrics.

20. The data storage device as recited in claim 17, wherein the controller is further configured to:

decode the interleaved codeword based on at least one channel code constraint.