Array substrate and method for manufacturing the same

• US 10,559,601 B2
• Filed: 06/23/2017
• Issued: 02/11/2020
• Est. Priority Date: 09/26/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Su, Tongshang, Cheng, Jun, Zhao, Ce, Zhou, Bin, Wang, Dongfang, Yuan, Guangcai
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US15/580,240
• Publication Number:
  US 20190221588A1
• Time in Patent Office: 963 Days
• Field of Search: None
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H10K 10/484 characterised by the channel regions
• CPC Class Codes: H10K 10/82 Electrodes
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.

Claims

1. An array substrate comprising:

at least a first region and a second region, each first region including a first thin film transistor and each second region including a second thin film transistor;

wherein a thickness of an active layer of the first thin film transistor in the first region is greater than that of an active layer of the second thin film transistor in the second region; and

wherein an overlapped area between a source electrode or a drain electrode and the active layer of the first thin film transistor in the first region is larger than that between a source electrode or a drain electrode and the active layer of the second thin film transistor in the second region, so that a ratio of the overlapped area between the source electrode or the drain electrode and the active layer to the thickness of the active layer for each of the first thin film transistor and the second thin film transistor is kept uniform over the first region and the second region.

2. The array substrate according to claim 1, wherein:

a length of an overlapped portion between the source electrode or the drain electrode and the active layer of the each of the first and second thin film transistors is a width of a channel region of the active layer, and a width of the overlapped portion is a fixed value; and

the ratio of the width of the channel region of the active layer to the thickness of the active layer for each of the first thin film transistor and the second thin film transistor is kept uniform over the first region and the second region.

3. The array substrate according to claim 2, wherein:

a curve of a variation of the thickness of the active layer of the first and/or second thin film transistor in at least one of the first region and the second region depending on a position of the active layer is represented by a fitting function, and

the width of the channel region of the active layer of the first and/or second thin film transistor in the at least one of the first region and the second region changes in proportion to the fitting function.

4. The array substrate according to claim 1, wherein the first region and the second region are periodically and alternately arranged.

5. The array substrate according to claim 1, wherein each of the first and second thin film transistors comprises a driving thin film transistor for applying a driving current to an organic light emitting diode and a switching thin film transistor for applying a driving voltage to the driving thin film transistor.

6. The array substrate according to claim 1, wherein each of the first and second thin film transistors comprises a switching thin film transistor for applying a data voltage to a liquid crystal layer.

15. The array substrate according to claim 2, wherein the first region and the second region are periodically and alternately arranged.

16. The array substrate according to claim 2, wherein the thin film transistor comprises a driving thin film transistor for applying a driving current to an organic light emitting diode and a switching thin film transistor for applying a driving voltage to the driving thin film transistor.

17. The array substrate according to claim 2, wherein the thin film transistor comprises a switching thin film transistor for applying a data voltage to a liquid crystal layer.

7. A method for manufacturing an array substrate, comprising steps of:

obtaining a variation of a thickness of an active layer depending on a position on a substrate, the active layer having at least a first region with a larger thickness and a second region with a second thickness, the first thickness being larger than the second thickness;

determining an overlapped area between a source electrode or a drain electrode and the active layer of a thin film transistor to be formed according to the variation such that a ratio of the overlapped area to the thickness of the active layer is kept uniform over the first region and the second region; and

forming the thin film transistor on the substrate such that the formed thin film transistor has the determined overlapped area.

8. The method according to claim 7, wherein:

a length of an overlapped portion between the source electrode or the drain electrode and the active layer of the thin film transistor is a width of a channel region of the active layer, and a width of the overlapped portion is a fixed value; and

the step of determining the overlapped area comprises;

determining the width of the channel region of the active layer to be formed such that the ratio of the width of the channel region of the active layer to the thickness of the active layer is kept uniform over the first region and the second region.

9. The method according to claim 7, wherein the step of obtaining the variation of the thickness of the active layer depending on the position on the substrate comprises:

forming an active film on a test substrate that is the same as the substrate; and

measuring a thickness of the active film in the first region and the second region.

10. The method according to claim 9, wherein the step of determining the overlapped area comprises:

determining a fitting function of a curve of the variation of the thickness of the active layer in at least one of the first region and the second region depending on the position of the active layer based on the measured thickness of the active film; and

determining the overlapped area in the at least one area such that the overlapped area varies in proportion to the fitting function.

11. The method according to claim 8, wherein the step of obtaining the variation of the thickness of the active layer depending on the position on the substrate comprises:

forming an active film on a test substrate that is the same as the substrate; and

measuring a thickness of the active film in the first region and the second region.

12. The method according to claim 11, wherein the step of determining the width of the channel region of the active layer to be formed comprises:

determining a fitting function of a curve of the variation of the thickness of the active layer in at least one of the first region and the second region depending on the position of the active layer based on the measured thickness of the active film; and

determining the width of the channel region of the active layer in the at least one region such that the width of the channel region of the active layer varies in proportion to the fitting function.

13. The method according to claim 7, wherein the step of forming the thin film transistor on the substrate comprises:

forming a gate electrode on the substrate;

forming a gate insulating layer on the gate electrode;

forming an active film on the gate insulating layer;

patterning the active film to form the active layer; and

forming the source electrode and the drain electrode on the active layer.

14. The method according to claim 13, wherein the variation is obtained and the overlapped area is determined after the active film or the active layer is formed.

18. An array substrate comprising a thin film transistor, wherein the array substrate comprises at least a first region and a second region;

a thickness of an active layer of the thin film transistor in the first region is greater than that of an active layer of the thin film transistor in the second region, and an overlapped area between a source electrode or a drain electrode and the active layer of the thin film transistor in the first region is larger than that between a source electrode or a drain electrode and the active layer of the thin film transistor in the second region, so that a ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region;

wherein a curve of a variation of the thickness of the active layer of the thin film transistor in at least one of the first region and the second region depending on a position of the active layer is represented by a fitting function, and the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor in the at least one of the first region and the second region changes in proportion to the fitting function.