NAND memory cell string having a stacked select gate structure and process for for forming same

• US 10,566,341 B2
• Filed: 06/25/2019
• Issued: 02/18/2020
• Est. Priority Date: 06/22/2009
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kwan, Ming Sang, Fang, Shenqing, Suh, Youseok, Van Buskirk, Michael A.
• Primary Examiner(s): Nguyen, Hien N
• Application Number:
  US16/452,106
• Publication Number:
  US 20190326303A1
• Time in Patent Office: 238 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

Claims

1. A memory string, comprising:

a channel formed in a cylinder of semiconducting material, extending vertically from source in a substrate to a drain overlying the substrate

a plurality of core cells serially connected along the channel between a source select gate and a drain select gate, each core cell including an internal wordline separated from the channel by a first stack of layers including a charge trapping layer; and

wherein the internal wordlines of the plurality of core cells are formed by alternating conducting and dielectric layers overlying the substrate and through which the channel extends.

2. The memory string of claim 1 wherein the cylinder of semiconducting material comprises a solid cylinder of polysilicon.

3. The memory string of claim 1 wherein the cylinder of semiconducting material comprises an annular cylinder of polysilicon surrounding a core of a dielectric material.

4. The memory string of claim 1 wherein the charge trapping layer comprises a nitride.

5. The memory string of claim 1 wherein at least one of the source and drain select gates is a stacked select gate comprising a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the plurality of core cells by the first component.

6. The memory string of claim 5 wherein the first component comprises a first gate separated from the channel by a second stack of layers having the same stoichiometric composition and thicknesses as the first stack of layers, and the second component comprises a second gate separated from the channel by a third stack of layers not including a charge trapping layer.

7. The memory string of claim 6 wherein the second gate of the second component is separated from the channel by a single layer gate dielectric.

8. The memory string of claim 6 wherein the first and second stack of layers comprise an oxide-nitride-oxide (ONO).

9. The memory string of claim 5 wherein the first gate of the first component and the second gate of the second component comprise a same size.

10. The memory string of claim 5 wherein the first gate of the first component and the second gate of the second component comprise a different size.

11. The memory string of claim 5 wherein the first gate is configured to be biased during an erase operation with an erase voltage to have a same bias environment as the internal wordlines of the plurality of core cells to provide erasure threshold voltage uniformity.

12. The memory string of claim 11 wherein the first gate and the internal wordlines are configured to be biased with a same erase voltage during an erase operation.