System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines

• US 10,572,824 B2
• Filed: 12/22/2016
• Issued: 02/25/2020
• Est. Priority Date: 05/23/2003
• Status: Active Grant

• Current Assignee: Ip Reservoir, LLC
• Original Assignee: Ip Reservoir, LLC
• Inventors: Chamberlain, Roger D., Franklin, Mark Allen, Indeck, Ronald S., Cytron, Ron K.
• Primary Examiner(s): Ly, Anh
• Application Number:
  US15/388,498
• Publication Number:
  US 20170102950A1
• Time in Patent Office: 1,160 Days
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 16/2455 Query execution
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06N 20/00 Machine learning

Abstract

A multi-functional data processing pipeline is disclosed where the multi-functional pipeline comprises a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations. The multi-functional pipeline can be configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. In example embodiments, the pipelined data processing engines can include correlation logic, and such pipelines can be used to accelerate convolutional layers in machine-learning technology such as convolutional neural networks.

Claims

1. A data processing system comprising:

a processor comprising a plurality of data processing engines arranged as a multi-functional pipeline through which data is streamed, the pipelined data processing engines configured for operation in parallel with each other;

each pipelined data processing engine being configured to (1) receive streaming data and perform a processing operation on the received streaming data, and (2) be responsive to a control instruction that defines whether that pipelined data processing engine is an activated data processing engine or a deactivated data processing engine, wherein an activated data processing engine is configured to perform the processing operation of that activated data processing engine on streaming data received thereby, and wherein a deactivated data processing engine remains in the pipeline but does not perform the processing operation of that deactivated data processing engine on streaming data received thereby, the multi-functional pipeline thereby being configured to provide a plurality of different pipeline functions in response to control instructions that are configured to selectively activate and deactivate the pipelined data processing engines, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline at a given time; and

wherein at least one of the pipelined data processing engines includes correlation logic that operates on first data and second data.

2. The system of claim 1 wherein the processor comprises a re-configurable logic device, and wherein the multi-functional pipeline resides on the re-configurable logic device.

3. The system of claim 2 wherein the re-configurable logic device comprises a field programmable gate array (FPGA), wherein the multi-functional pipeline resides on the FPGA.

4. The system of claim 3 wherein the correlation logic is configured to operate on the second data over a sliding window of the first data.

5. The system of claim 4 wherein the first data and the second data comprise digital data.

6. The system of claim 5 wherein the data processing engine that includes the correlation logic further includes a data shift register through which the first data is streamed.

7. The system of claim 6 wherein the data processing engine that includes the correlation logic and the data shift register further includes a register that holds the second data, wherein the data shift register and the register comprise a plurality of cells, and

wherein the correlation logic comprises digital logic connected to the cells of the data shift register and the register that performs logical operations on the first data and second data within the connected cells.

8. The system of claim 7 wherein the digital logic comprises multiply and accumulate logic connected to each other to compute a running sum of multiplied values.

9. The system of claim 8 wherein the multiply and accumulate logic comprises a plurality of multipliers connected to the cells and summation logic connected to a plurality of outputs of the multipliers.

10. The system of claim 1 wherein the data processing engine that includes the correlation logic is further configured to correlate the first data with the second data via the correlation logic.

11. The system of claim 1 wherein the multi-functional pipeline is further configured to disconnect power from a deactivated data processing engine while retaining power to the activated data processing engines.

12. A data processing method comprising:

receiving a plurality of control instructions at a processor, the processor comprising a plurality of data processing engines arranged as a multi-functional pipeline through which data is streamed, the pipelined data processing engines configured for operation in parallel with each other, each pipelined data processing engine being configured to (1) receive streaming data and perform a processing operation on the received streaming data, and (2) be responsive to a control instruction that defines whether that pipelined data processing engine is an activated data processing engine or a deactivated data processing engine, wherein an activated data processing engine is configured to perform the processing operation of that activated data processing engine on streaming data received thereby, and wherein a deactivated data processing engine remains in the pipeline but does not perform the processing operation of that deactivated data processing engine on streaming data received thereby, the multi-functional pipeline thereby being configured to provide a plurality of different pipeline functions in response to control instructions that are configured to selectively activate and deactivate the pipelined data processing engines, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline at a given time, and wherein at least one of the pipelined data processing engines includes correlation logic that operates on first data and second data;

activating and deactivating the pipelined data processing engines in accordance with the received control instructions, wherein at least one of the activated pipelined data processing engines comprises at least one of the pipelined data processing engines that includes the correlation logic; and

the activated pipelined data processing engines in the multi-functional pipeline performing their data processing operations on data received thereby.

13. The method of claim 12 wherein the processor comprises a re-configurable logic device, and wherein the multi-functional pipeline resides on the re-configurable logic device.

14. The method of claim 13 wherein the re-configurable logic device comprises a field programmable gate array (FPGA), wherein the multi-functional pipeline resides on the FPGA.

15. The method of claim 14 wherein the correlation logic operates on the second data over a sliding window of the first data.

16. The method of claim 15 wherein the first data and the second data comprise digital data.

17. The method of claim 16 wherein the data processing engine that includes the correlation logic further includes a data shift register through which the first data is streamed.

18. The method of claim 17 wherein the data processing engine that includes the correlation logic and the data shift register further includes a register that holds the second data, wherein the data shift register and the register comprise a plurality of cells, and

wherein the correlation logic comprises digital logic connected to the cells of the data shift register and the register, the digital logic performing logical operations on the first data and second data within the connected cells.

19. The method of claim 18 wherein the digital logic comprises multiply and accumulate logic connected to each other to compute a running sum of multiplied values.

20. The method of claim 19 wherein the multiply and accumulate logic comprises a plurality of multipliers connected to the cells and summation logic connected to a plurality of outputs of the multipliers.

21. The method of claim 12 wherein an activated data processing engine that includes the correlation logic correlates the first data with the second data via the correlation logic.

22. The method of claim 12 wherein the deactivating step comprises disconnecting power from a deactivated data processing engine within the multi-functional pipeline.