Bondpad integrated thermoelectric cooler

• US 10,573,578 B2
• Filed: 03/13/2013
• Issued: 02/25/2020
• Est. Priority Date: 08/29/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Edwards, Henry L.
• Primary Examiner(s): Dam, Dustin Q
• Application Number:
  US13/798,592
• Publication Number:
  US 20130187252A1
• Time in Patent Office: 2,540 Days
• Field of Search: None
• CPC Class Codes: F25B 21/02 using Peltier effect; using Nernst-Ettinghausen effect
• CPC Class Codes: F25B 2321/021 Control thereof
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05094 at the center of the internal layers
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 23/38 Cooling arrangements using the Peltier effect
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H10N 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00

Abstract

An integrated circuit has thermoelectric cooling devices integrated into bondpads. A method for operating the integrated circuit includes turning a thermal switch to a thermoelectric cooler operate position when the integrated circuit is powered up, turning the thermal switch to a thermoelectric cooler operate position to allow the thermoelectric cooler to operate when the integrated circuit powers down, and turning the thermal switch to a thermoelectric cooler off position when a predetermined integrated circuit chip temperature is reached.

Claims

1. An integrated circuit, comprising:

a bondpad; and

a thermoelectric cooler coupled to the bondpad, the thermoelectric cooler comprising thermopiles with at least one horizontal dimension less than 300 nm.

6. The integrated circuit of claim 1, further comprising:

interconnect layers; and

a low thermoconductivity dielectric material in the interconnect layers.

7. The integrated circuit of claim 1, further comprising a thermal switch circuit coupled to the thermoelectric cooler.

2. An integrated circuit, comprising:

a first bondpad;

a second bondpad;

a thermoelectric cooler comprising;

an n-type thermoelectric cooler coupled to the first bondpad, the n-type thermoelectric cooler formed in an n-doped well and composed of n-type active areas with at least one horizontal dimension less than 300 nm; and

a p-type thermoelectric cooler coupled to the second bondpad, the p-type thermoelectric cooler formed in a p-doped well and composed of p-type active areas with at least one horizontal dimension less than 300 nm; and

a thermal switch circuit coupled to the thermoelectric cooler.

3. The integrated circuit of claim 2, further comprising:

interconnect layers; and

a low thermoconductivity dielectric material in the interconnect layers.

4. An integrated circuit, comprising:

a first bondpad;

a second bondpad;

an n-type thermoelectric cooler composed of n-type active areas with at least one horizontal dimension less than 300 nm formed in an n-doped well and coupled to the first bondpad; and

a p-type thermoelectric cooler composed of p-type active areas with at least one horizontal dimension less than 300 nm formed in a p-doped well and coupled to the second bondpad.

5. The integrated circuit of claim 4, further comprising:

interconnect layers; and

a low thermoconductivity dielectric material in the interconnect layers.

8. The integrated circuit of claim 4, further comprising a thermal switch circuit coupled to the n-type thermoelectric cooler and to the p-type thermoelectric cooler.