Three-dimensional memory device and methods of making the same using replacement drain select gate electrodes

• US 10,586,803 B2
• Filed: 06/29/2018
• Issued: 03/10/2020
• Est. Priority Date: 04/24/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Mushiga, Mitsuteru, Otoi, Hisakazu, Sugiura, Kenji, Cui, Zhixin, Sakakibara, Kiyohiko
• Primary Examiner(s): Ojeh, Nduka E
• Application Number:
  US16/023,289
• Publication Number:
  US 20190326306A1
• Time in Patent Office: 620 Days
• Field of Search: 257314
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

Claims

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

drain-select-level electrically conductive strips located over the alternating stack;

a drain-select-level isolation structure located between a neighboring pair of the drain-select-level electrically conductive strips;

memory stack structures comprising a respective memory film and a respective vertical semiconductor channel vertically extending through the alternating stack and a respective one of the drain-select-level electrically conductive strips, wherein the memory stack structures contact, and are completely laterally surrounded by, a cylindrical sidewall of a respective one of the drain-select-level electrically conductive strips;

a contact level dielectric layer overlying the drain-select-level electrically conductive strips, the drain-select-level isolation structure and the memory stack structures, wherein the contact level dielectric layer contacts the drain-select-level isolation structure; and

at least one feature selected from;

(i) a first feature further comprising drain regions located at a top end of a respective one of the memory stack structures,

wherein;

a bottom periphery of each of the drain regions coincides with a topmost periphery of an outer sidewall of an underlying one of the memory stack structures; and

sidewalls of the drain-select-level electrically conductive strips are in contact with sidewalls of the memory stack structures, and are vertically coincident with sidewalls of the drain regions;

or

(ii) a second feature wherein each of the drain-select-level electrically conductive strips has a respective laterally alternating sequence of planar vertical sidewall segments and convex vertical sidewall segments, wherein each convex vertical sidewall segment is laterally spaced from a most proximal one of the memory stack structures by a uniform lateral spacing;

or

(iii) a third feature wherein each of the drain-select-level electrically conductive strips has a top surface located below a horizontal plane including a top surface of the drain-select-level isolation structure; and

each of the drain-select-level electrically conductive strips has a bottom surface located within a horizontal plane including a bottom surface of the drain-select-level isolation structure;

or

(iv) a fourth feature wherein;

the memory stack structures are arranged as rows that laterally extend with a uniform pitch along a first horizontal direction; and

the three-dimensional memory device further comprises an insulating cap strip located over the alternating stack and having a straight sidewall that extend along the first horizontal direction by at least twice the uniform pitch;

or

(v) a fifth feature wherein;

the drain-select-level isolation structure generally extends along a first horizontal direction; and

the drain-select-level isolation structure includes a pair of laterally alternating sequences of planar vertical sidewall segments and concave vertical sidewall segments that alternate along the first horizontal direction.

2. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device comprises the first feature.

3. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device comprises the second feature.

4. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device comprises the third feature.

5. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device comprises the fourth feature.

6. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device comprises the fifth feature.

7. The three-dimensional memory device of claim 6, wherein each of the concave vertical sidewall segments is laterally spaced from a respective most proximal one of the memory stack structures by a uniform lateral spacing.

8. The three-dimensional memory device of claim 7, wherein the uniform lateral spacing is the same as a lateral width of peripheral portions of the drain-select-level electrically conductive strips disposed between the drain-select-level isolation structure and most proximal ones among the memory stack structures.

9. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

drain-select-level electrically conductive strips located over the alternating stack;

a drain-select-level isolation structure located between a neighboring pair of the drain-select-level electrically conductive strips;

memory stack structures comprising a respective memory film and a respective vertical semiconductor channel vertically extending through the alternating stack and a respective one of the drain-select-level electrically conductive strips, wherein the memory stack structures contact, and are completely laterally surrounded by, a cylindrical sidewall of a respective one of the drain-select-level electrically conductive strips; and

a contact level dielectric layer overlying the drain-select-level electrically conductive strips, the drain-select-level isolation structure and the memory stack structures, wherein the contact level dielectric layer contacts the drain-select-level isolation structure,

wherein;

each of the drain-select-level electrically conductive strips comprises a respective metallic nitride liner and a respective metallic fill material portion;

each metallic nitride liner consists essentially of a conductive metal nitride; and

each metal fill material portion consists essentially of an elemental metal or an intermetallic alloy.

10. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

drain-select-level electrically conductive strips located over the alternating stack;

a drain-select-level isolation structure located between a neighboring pair of the drain-select-level electrically conductive strips;

memory stack structures comprising a respective memory film and a respective vertical semiconductor channel vertically extending through the alternating stack and a respective one of the drain-select-level electrically conductive strips, wherein the memory stack structures contact, and are completely laterally surrounded by, a cylindrical sidewall of a respective one of the drain-select-level electrically conductive strips;

a contact level dielectric layer overlying the drain-select-level electrically conductive strips, the drain-select-level isolation structure and the memory stack structures, wherein the contact level dielectric layer contacts the drain-select-level isolation structure;

dielectric cores embedded within a respective one of the vertical semiconductor channels and including a respective upper cylindrical portion embedded within the drain-select-level electrically conductive strips; and

core cavities embedded within a respective one of the dielectric cores and having a maximum lateral dimension that is greater than a maximum lateral dimension of an overlying one of the upper cylindrical portions of the dielectric cores.