Display panel having conductive layer in peripheral area and barriers for preventing air bubble

• US 10,591,780 B2
• Filed: 12/12/2016
• Issued: 03/17/2020
• Est. Priority Date: 06/13/2016
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Li, Yang, Liu, Hua, Feng, Bin, Sun, Peng, Shi, Huzhao
• Primary Examiner(s): Ngo, Huyen L
• Application Number:
  US15/534,156
• Publication Number:
  US 20180196296A1
• Time in Patent Office: 1,191 Days
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/13396 Spacers having different sizes
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

A display panel is provided. The display panel includes a conductive layer having a plurality of protrusions alternating with a plurality of indentations along a side proximal to the interface between the display area and the peripheral area. The plurality of protrusions protrudes in a direction from the peripheral area to the display area. The plurality of indentations indented in a direction from the display area to the peripheral area. Adjacent protrusions spaced apart by an indentation. The display panel further includes a plurality of common electrode signal lines. Each of the plurality of common electrode signal lines extends from an apex of each of the plurality of protrusions into the display area for providing a common voltage. A plurality of openings in the first barrier and the second barrier are substantially aligned with the plurality of indentations.

Claims

1. A display panel having a display area and a peripheral area, comprising a counter substrate and an array substrate facing the counter substrate, the array substrate comprising a conductive layer on a first base substrate of the array substrate in the peripheral area;

wherein the counter substrate comprises;

a second base substrate; and

a barrier layer on the second base substrate in the peripheral area comprising a barrier having a first side proximal to an interface between the display area and the peripheral area and a second side distal to the interface between the display area and the peripheral area;

the first side having a first undulating shape;

the second side having a second undulating shape;

wherein the barrier comprises a plurality of barrier segments, two adjacent barrier segments are spaced apart from each other forming an opening between the two adjacent barrier segments of the barrier;

at least one of the plurality of barrier segments having a bend protruding towards the interface between the display area and the peripheral area, thereby forming a convex surface on the first side and a concave surface on the second side;

wherein the barrier layer comprises a plurality of barriers;

each of the plurality of barriers has a first side proximal to the interface between the display area and the peripheral area and a second side distal to the interface between the display area and the peripheral area;

the first side having a first undulating shape;

the second side having a second undulating shape;

each of the plurality of barriers comprises a plurality of barrier segments arranged substantially in a direction parallel to the interface between the display area and the peripheral area, two adjacent barrier segments of each of the plurality of barriers being spaced apart from each other forming an opening between the two adjacent barrier segments of each of the plurality of barriers; and

each of the plurality of barrier segments of each of the plurality of barriers comprises a bend protruding towards the interface between the display area and the peripheral area, thereby forming a convex surface on the first side and a concave surface on the second side in each of the plurality of barrier segments of each of the plurality of barriers;

wherein the plurality of barriers comprises a first barrier and a second barrier;

a projection of the first barrier on the first base substrate of the array substrate being outside a projection of the conductive layer on the first base substrate;

a projection of the second barrier on the first base substrate of the array substrate overlapping with the projection of the conductive layer on the first base substrate;

wherein the conductive layer has a plurality of protrusions alternating with a plurality of indentations along a side proximal to the interface between the display area and the peripheral area, the plurality of protrusions protruding in a direction from the peripheral area to the display area, the plurality of indentations indented in a direction from the display area to the peripheral area;

adjacent protrusions spaced apart by an indentation;

the array substrate further comprises a plurality of common electrode signal lines;

each of the plurality of common electrode signal lines extending from an apex of each of the plurality of protrusions into the display area for providing a common voltage; and

a plurality of openings in the first barrier and the second barrier are substantially aligned with the plurality of indentations.

2. The display panel of claim 1, wherein the conductive layer is provided with a common voltage.

3. The display panel of claim 1, each of the first barrier and the second barrier has a first terminal and a second terminal;

the second terminal is on a side of the first terminal closer to the first base substrate of the counter substrate; and

a shortest distance between the first terminal of the first barrier and a surface of the array substrate is greater than a shortest distance between the first terminal of the second barrier and the surface of the array substrate.

4. The display panel of claim 1, wherein the array substrate comprises a gate insulating layer, a gate line layer having a plurality of gate lines on the gate insulating layer, an interlayer dielectric layer on a side of the gate line layer distal to the gate insulating layer, and the conductive layer on a side of the interlayer dielectric layer distal to the gate line layer;

wherein a portion of the conductive layer on a side of each of the plurality of gate lines is elevated relative to a surface of a remaining portion of the conductive layer thereby forming a plurality of grooves on a surface of the conductive layer;

each of the plurality of grooves sandwiched between two adjacent portions of the conductive layer that are elevated.

5. The display panel of claim 4, wherein a plurality of portions of the conductive layer that are elevated are substantially aligned with the plurality of protrusions;

and

the plurality of grooves are substantially aligned with the plurality of indentations.

6. The display panel of claim 1, wherein each of the plurality of barrier segments comprises the bend protruding towards the interface between the display area and the peripheral area, thereby forming the convex surface on the first side and the concave surface on the second side in each of the plurality of barrier segments.

7. The display panel of claim 1, wherein the at least one of the plurality of barrier segments has a linear shaped cross-section along a plane parallel to the first base substrate.

8. The display panel of claim 7, wherein the at least one of the plurality of barrier segments comprises a first portion and a second portion joined at an angle thereby forming the bend;

cross-sections of the first portion and the second portion along the plane parallel to the first base substrate are joined at the angle.

9. The display panel of claim 1, wherein a plurality of openings respectively between adjacent barrier segments in a respective one of the plurality of barriers are respectively substantially aligned with a plurality of openings respectively between adjacent barrier segments in an adjacent barrier of the plurality of barriers.

10. The display panel of claim 1, wherein a plurality of openings in one of the plurality of barriers are offset from those in an adjacent barrier.

11. The display panel of claim 1, wherein the conductive layer is provided with a common voltage.

12. The display panel of claim 1, each of the first barrier and the second barrier has a first terminal and a second terminal;

the second terminal is on a side of the first terminal closer to the first base substrate of the counter substrate; and

a shortest distance between the first terminal of the second barrier and the first base substrate is smaller than a shortest distance between the first terminal of the first barrier and the first base substrate.