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Transducer clock signal distribution

  • US 10,591,951 B2
  • Filed: 04/25/2018
  • Issued: 03/17/2020
  • Est. Priority Date: 03/15/2013
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • receiving a clock signal at a first tile controller buffer of a plurality of tile controller buffers;

    receiving the clock signal received at the first tile controller buffer at a second tile controller buffer and a third tile controller buffer at substantially the same time from the first tile controller buffer, the second tile controller buffer being horizontally adjacent to the first tile controller buffer and the third tile controller buffer being vertically adjacent to the first tile controller buffer; and

    receiving the clock signal received at the first tile controller buffer at a fourth controller buffer from the first tile controller buffer and the clock signal received at the second tile controller buffer at the fourth tile controller buffer, the fourth tile controller buffer being horizontally adjacent to the third tile controller buffer and vertically adjacent to the second tile controller buffer.

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