Safety hypervisor function

• US 10,592,270 B2
• Filed: 10/16/2017
• Issued: 03/17/2020
• Est. Priority Date: 02/21/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Brewerton, Simon, Farrall, Glenn, Hastie, Neil, Hellwig, Frank, Knight, Richard, Vilela, Antonio
• Primary Examiner(s): Shin, Christopher B
• Application Number:
  US15/784,528
• Publication Number:
  US 20180039508A1
• Time in Patent Office: 883 Days
• Field of Search: 710308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2009/45587 Isolation or security of virtual machine instances
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Claims

1. A system that provides access protection, the system comprising:

a computer processing unit (CPU) configured to encode a safety privilege level as a property of a transaction executed by the CPU, wherein the safety privilege level is indicative of safety properties suported by the CPU;

a bus coupling the CPU to local data memory; and

a bus memory protection unit (bus MPU) configured to;

store a bus private configuration describing one or more authorized safety privilege levels for the bus;

receive the transaction;

identify the the safety privilege level encoded as the property of the transaction;

compare the safety privilege level with the bus private configuration; and

grant access to the local data memory in response to determining that the safety privilege level matches one of the authorized safety privilege levels for the bus.

2. The system of claim 1, wherein the CPU includes a register that stores the safety privilege level.

3. The system of claim 1, wherein the safety privilege level is a safety bit.

4. The system of claim 1, wherein the safety privilege level is a safety code.

5. The system of claim 1, wherein the safety privilege level is pre-determined.

6. The system of claim 1, wherein an operating system running on the CPU dynamically allocates the safety privilege level to one or more CPU hardware structures.

13. The system of claim 1, wherein the CPU is configured to encode the safety privilege level as a device identifier associated with the transaction.

14. The system of claim 1, wherein the bus MPU is configured to grant access corresponding to one of read-only, write-only, and read/write.

7. A system that provides access protection, the system comprising:

a computer processing unit (CPU) configured to encode a safety privilege level as a property of a transaction executed by the CPU, wherein the safety privilege level is indicative of safety properties suported by the CPU;

a register coupled to the CPU;

a register memory protection unit (register MPU) configured to;

store a register private configuration describing one or more authorized safety privilege levels for the register;

receive the transaction;

identify the the safety privilege level encoded as the property of the transaction;

compare the safety privilege level with the register private configuration; and

grant access to the register in response to determining that the safety privilege level matches one of the authorized safety privilege levels for the register.

8. The system of claim 7, wherein the register MPU is configured to compare the safety privilege level with a safety privilege level for a peripheral associated with the transaction.

9. The system of claim 8, wherein the register MPU is configured to grant access to the register based on the comparison of the safety privilege level for the task and the safety privilege level for the peripheral.

10. The system of claim 7, wherein the register MPU is configured to grant access having a protection granularity, wherein the protection granularity includes one of read-only, write-only, and read/write.

11. The system of claim 7, wherein the register MPU grants access corresponding to one of read only, write only, and/or read/write.

12. The system of claim 7, further comprising a peripheral register MPU that allows exclusive access to a peripheral for the transaction based on the safety privilege level.

15. The system of claim 7, wherein the CPU includes a register that stores the safety privilege level.

16. The system of claim 7, wherein the safety privilege level is a safety bit.

17. The system of claim 7, wherein the safety privilege level is a safety code.

18. The system of claim 7, wherein the CPU is configured to encode the safety privilege level as a device identifier associated with the transaction.