RF switches, integrated circuits, and devices with multi-gate field effect transistors and voltage leveling circuits, and methods of their fabrication

• US 10,593,800 B2
• Filed: 04/30/2019
• Issued: 03/17/2020
• Est. Priority Date: 02/28/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Malladi, Venkata Naga Koushik
• Primary Examiner(s): Ahmed, Shahed
• Application Number:
  US16/398,992
• Publication Number:
  US 20190267489A1
• Time in Patent Office: 322 Days
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0733 in combination with capacitors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a pair of the gate structures. A first capacitor is electrically coupled between the channel contact and the source terminal, and a second capacitor is electrically coupled between the channel contact and the drain terminal.

Claims

1. A method of fabricating a field effect transistor (FET) circuit, the method comprising:

forming a FET in and over an active surface of a semiconductor substrate by

coupling a source terminal to the active surface,

coupling a drain terminal to the active surface, wherein a multi-gate FET channel is present in the semiconductor substrate between the source and drain terminals, and

coupling a plurality of gate structures to the active surface over the multi-gate FET channel;

coupling a first channel contact to the active surface over the multi-gate FET channel between a first pair of gate structures of the plurality of gate structures;

electrically coupling a first capacitor between the first channel contact and the source terminal; and

electrically coupling a second capacitor between the first channel contact and the drain terminal.

2. The method of claim 1, wherein:

forming the FET further comprises coupling a second channel contact to the active surface between a second pair of gate structures of the plurality of gate structures, and the method further comprises;

electrically coupling a third capacitor between the first and second channel contacts.

3. The method of claim 1, further comprising:

electrically coupling a third capacitor between the first channel contact and a gate structure of the plurality of gate structures.

4. The method of claim 1, further comprising:

coupling a first resistor between the first channel contact and the source terminal in parallel with the first capacitor; and

coupling a second resistor between the first channel contact and the drain terminal in parallel with the second capacitor.

5. The method of claim 4, further comprising:

coupling a second channel contact to the active surface between a second pair of the gate structures; and

electrically coupling a third capacitor between the first and second channel contacts.

6. The method of claim 4, wherein the first and second resistors are stripline resistors that are integrally formed with the semiconductor substrate over the active surface.

7. The method of claim 4, wherein the first and second resistors each have a resistance value in a range of 2 kiloohms to 60 kiloohms.

8. The method of claim 1, further comprising:

electrically coupling a third capacitor between the source terminal and a second gate structure of the plurality of gate structures, where the second gate structure may be the same as or different from the first gate structure.

9. The method of claim 1, wherein the first and second capacitors each have a capacitance value in a range of 0.05 picofarads to 5.0 picofarads.

10. The method of claim 1, wherein the first channel contact is an ohmic contact.

11. The method of claim 1, wherein the first and second capacitors each are a metal-insulator-metal capacitor that is integrally formed with the semiconductor substrate over the active surface.

12. The method of claim 1, wherein the semiconductor substrate is selected from a group that includes a gallium arsenide substrate, a silicon substrate, a silicon-on-insulator CMOS substrate, a bulk silicon CMOS substrate, a gallium nitride substrate, a gallium nitride-on-silicon substrate, and a gallium nitride on silicon carbide substrate.

13. A method of fabricating a radio frequency switch, the method comprising:

electrically coupling a first field effect transistor (FET) between an antenna node and a first transmit/receive (T/R) node, wherein the first FET includes

a semiconductor substrate with an active surface,

a source terminal coupled to the active surface,

a drain terminal coupled to the active surface,

a multi-gate FET channel in the semiconductor substrate between the source and drain terminals, and

a plurality of gate structures coupled to the active surface over the multi-gate FET channel;

coupling a first channel contact to the active surface over the multi-gate FET channel between a first pair of gate structures of the plurality of gate structures;

electrically coupling a first capacitor between the first channel contact and the source terminal; and

electrically coupling a second capacitor between the first channel contact and the drain terminal.

14. The method of claim 13, further comprising:

coupling a second channel contact to the active surface between a second pair of gate structures of the plurality of gate structures; and

electrically coupling a third capacitor between the first and second channel contacts.

15. The method of claim 13, further comprising:

electrically coupling a third capacitor between the first channel contact and a gate structure of the plurality of gate structures.

16. The method of claim 13, further comprising:

coupling at least one additional FET in series with the first FET between the antenna node and the first T/R node.

17. The method of claim 13, further comprising:

coupling a second FET between the first T/R node and a voltage reference terminal.

18. The method of claim 17, further comprising:

coupling at least one additional FET in series with the second FET between the first T/R node and the voltage reference terminal.

19. The method of claim 13, further comprising:

coupling a second FET between the antenna node and a second T/R node.

20. The method of claim 19, further comprising:

coupling a third FET between the first T/R node and a voltage reference terminal; and

coupling a fourth FET between the second T/R node and the voltage reference terminal.