Nanofluid sensor with real-time spatial sensing

• US 10,605,768 B2
• Filed: 08/08/2017
• Issued: 03/31/2020
• Est. Priority Date: 12/31/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Shahidi, Ghavam G., Shahrjerdi, Davood
• Primary Examiner(s): Parendo, Kevin
• Application Number:
  US15/671,949
• Publication Number:
  US 20170336349A1
• Time in Patent Office: 966 Days
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4146 involving nanosized elements, e.g. nanotubes, nanowires
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.

Claims

1. A method of forming a nanofluid sensor for sensing nanoparticles in a nanofluid, said method comprising:

forming an array of gate structures on a portion of a topmost semiconductor layer of a semiconductor-on-insulator substrate, wherein each gate structure is a component of a transistor and said semiconductor-on-insulator substrate comprises, from bottom to top, a handle substrate, an insulator layer and said topmost semiconductor material layer;

exposing, after forming said array of gate structures, portions of said handle substrate of said semiconductor-on-insulator substrate at both ends of said array of gate structures;

forming an interlevel dielectric material in directly physical contact with said exposed portions of said handle substrate and surrounding said array of gate structures;

forming a vertical channel on each side of the array of gate structures and within said interlevel dielectric material, wherein said forming of the vertical channels physically exposes sidewall surfaces of said insulator layer of said semiconductor-on-insulator substrate that is positioned directly beneath said array of gate structures, and wherein each vertical channel has an opening located at a topmost surface;

removing said insulator layer that is positioned directly beneath said array of gate structures to provide a horizontal channel in fluid communication with said vertical channels, wherein said vertical channels and said horizontal channel are configured to accept said nanofluid containing said nanoparticles; and

forming a back gate dielectric material portion lining exposed surfaces within said verticals channel, and said horizontal channel.

2. The method of claim 1, wherein said forming said array of gate structures comprises:

providing said semiconductor-on-insulator substrate; and

forming a plurality of sacrificial gate structures on said topmost surface of said semiconductor-on-insulator substrate.

3. The method of claim 1, wherein said forming said array of gate structures comprises:

providing said semiconductor-on-insulator substrate; and

forming a plurality of functional gate structures on said topmost surface of said semiconductor-on-insulator substrate.

4. The method of claim 1, wherein said forming said vertical channels within said interlevel dielectric material to expose sidewall surfaces of said insulator layer of said semiconductor-on-insulator that is positioned directly beneath said array of gate structures comprises lithography and etching.

5. The method of claim 1, wherein said removing said insulator layer that is positioned directly beneath said array of gate structures comprises etching.

6. The method of claim 1, wherein said forming said back gate dielectric material portion comprises conformal depositing a layer of a back gate dielectric material.

7. The method of claim 6, further comprising removing said layer of back gate dielectric material from a topmost surface of said interlevel dielectric material.

8. The method of claim 1, wherein said back gate dielectric material portion extends to at least a topmost surface of said interlevel dielectric material.