Nonvolatile memory devices and methods of controlling the same

• US 10,606,760 B2
• Filed: 08/23/2017
• Issued: 03/31/2020
• Est. Priority Date: 08/23/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Erez, Elona, Dor, Avner, Twitto, Moshe, Kong, Jun Jin
• Primary Examiner(s): Wong, Nanci N
• Application Number:
  US15/684,252
• Publication Number:
  US 20190065392A1
• Time in Patent Office: 951 Days
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

Claims

1. A method of writing data to a memory system comprising:

receiving, by a memory controller, a sequence of N consecutive logical block addresses (LBAs) and logical sector data for each of the LBAs, from a host;

compressing, by the memory controller, the logical sector data;

executing, by the memory controller, a first one of a plurality of hash functions on a first LBA among the sequence to generate a first virtual address;

determining, by the memory controller, whether the first virtual address is occupied;

setting a destination address to the first virtual address when it is determined that the virtual address is not occupied;

setting the destination address to a second other virtual address generated from executing a second other one of the hash functions on the first LBA when it is determined that the first virtual address is occupied;

storing, the compressed data in a first physical sector of a nonvolatile memory associated with the destination address;

updating, by the memory controller, a mapping table to include to include a 1^st entry corresponding to the first LBA and an index of the hash function that generated the destination address, and 2^nd though Nth consecutive entries respectively corresponding to the 2^nd through Nth LBAs each including the index and an offset to the 1^st entry, and

where N is at least two.

2. The method of claim 1, wherein each hash function is configured to generate a different pseudo-random number when operated on a same LBA.

3. The method of claim 1, further comprising the memory controller storing information in spare region of the first physical sector indicating offsets and lengths of compressed logical sector data for each of the LBAs.

4. The method of claim 1, further comprising the memory controller updating the entries to indicate that logical sector data associated with each of the LBAs has been compressed.

5. A memory system comprising:

a nonvolatile memory device comprising a plurality of physical sectors;

a mapping table; and

a memory controller including a plurality of hash functions, the memory controller configured to access the physical sectors using the mapping table and the hash functions,

wherein the memory controller is configured to receive a sequence of N consecutive logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, compress the logical sector data to generate compressed data, execute a first one of the hash functions on a first logical block address (LBA) among the sequence to generate a first virtual address, determine whether the first virtual address is occupied, set a destination address to the first virtual address when it is determined that the first virtual address is not occupied, set the destination address to a second other virtual address generated from executing a second other one of the hash functions on the first LBA when it is determined that the first virtual address is occupied, and store the compressed data in a first physical sector among the physical sectors that is associated with the destination address,

wherein the memory controller updates the mapping table to include a 1^st entry corresponding to the first LBA and an index of the hash function that generated the destination address, and 2^nd though Nth consecutive entries respectively corresponding to the 2^nd through Nth LBAs each including the index and an offset to the 1^st entry, and

where N is at least two.

6. The memory system of claim 5, wherein each hash function is configured to generate a different pseudo-random number when operated on a same LBA.

7. The memory system of claim 5, wherein the controller is configured to receive an input LBA and a read command from the host, access an entry of the mapping table associated with the input LBA to retrieve an index and an offset, subtract the retrieved offset from the input LBA to generate a result, operate one of the hash functions identified by the retrieved index on the result to generate a third virtual address, and output data of one of the physical sectors associated with the third virtual address to the host.

8. The memory system of claim 5, wherein the nonvolatile memory is flash memory.

9. The memory system of claim 5, wherein the controller stores information in a spare region of the first physical sector indicating offsets and lengths of compressed logical sector data for each of the LBAs.

10. The memory system of claim 5, wherein the controller is configured to update the entries to indicate that logical sector data associated with each of the LBAs has been compressed.

11. The memory system of claim 5, wherein the controller is configured to receive an input LBA, store logical sector data associated with the input LBA in the memory device without compression in one of the physical sectors when the input LBA is received without at least one additional LBA sequential to the input LBA, and update an entry of the mapping table corresponding to the input LBA to indicate the stored logical sector data is uncompressed.

12. The memory system of claim 5, wherein the controller stores the compressed data in the first physical sector and a second physical sector among the physical sectors.

13. The memory system of claim 12, wherein the compressed data includes compressed data for one logical sector that is split across the first and second physical sectors.

14. The memory system of claim 13, wherein the controller updates the mapping table to indicate that the one logical sector is split.

15. The memory system of claim 5, further comprising a buffer temporarily storing the sequence of logical block addresses (LBAs) and the corresponding logical sector data.

16. A method of reading data from a memory system comprising:

receiving, by a memory controller, a first logical block address (LBA) and a read command from a host;

accessing, by the memory controller, an entry of a mapping table associated with the first LBA to retrieve an index and an offset, in response to receipt of the read command;

generating, by the memory controller, a second LBA by subtracting the offset from the first LBA;

selecting, by the memory controller, a hash function from among a plurality of different hash functions using the index;

executing, by the memory controller, the selected hash function on the second LBA to generate a virtual address; and

retrieving data from a physical sector of a nonvolatile memory associated with the virtual address,

wherein the different hash functions generate a different virtual address when executed on a same value.

17. The method of claim 16, further comprising:

uncompressing, by the memory controller, the retrieved data to generate uncompressed data when the entry indicates a compression has been performed;

sending, by the controller, the uncompressed data associated with the LBA to the host when the entry indicates the compression; and

sending, by the controller, the retrieved data to the host when the entry indicates no compression has been performed.

18. The method of claim 16, wherein the retrieving of the data comprises:

determining, by the memory controller, an offset and a size of the data in the physical sector from a spare region in the physical sector; and

extracting, by the memory controller, data from the physical sector at the offset and having the size.