Thin film transistor, array substrate and display device

• US 10,622,483 B2
• Filed: 05/19/2016
• Issued: 04/14/2020
• Est. Priority Date: 04/05/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Wang, Meili, Yan, Liangchen
• Primary Examiner(s): Dang, Phuc T
• Application Number:
  US15/529,645
• Publication Number:
  US 20180190831A1
• Time in Patent Office: 1,426 Days
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

The present disclosure provides a Thin Film Transistor and a method for manufacturing the same, an array substrate and a display device, so as to increase on-state currents of the Thin Film Transistor and improve current characteristics of the Thin Film Transistor. The Thin Film Transistor includes a base substrate, a gate insulating layer and a gate disposed above the base substrate; wherein a conductive layer is also disposed between the gate insulating layer and the gate; wherein the projection of the conductive layer on the base substrate is larger than the projection of the gate on the base substrate.

Claims

1. A Thin Film Transistor comprising:

a base substrate, a gate insulating layer and a gate disposed above the base substrate, and an active layer disposed between the base substrate and the gate insulating layer, wherein there is an offset area in a channel between the gate and the active layer;

a conductive layer disposed between the gate insulating layer and the gate; and

a source area electrically connected with a source to be formed and a drain area electrically connected with a drain to be formed, which are located on the same layer as the active layer and are oppositely arranged to each other,

wherein a projection of the gate on the base substrate, a projection of the conductive layer on the base substrate and a projection of the active layer on the base substrate partially overlap with one another, the projection of the conductive layer on the base substrate is larger than the projection of the gate on the base substrate, and

the projection of the active layer on the base substrate is larger than the projection of the conductive layer on the base substrate.

2. The Thin Film Transistor according to claim 1, wherein the conductive layer is made of one or more materials of a carbon material, metallic material and metallic oxide which are conductive.

3. The Thin Film Transistor according to claim 1, further comprising the source and the drain located above the gate.

4. The Thin Film Transistor according to claim 3, further comprising an interlayer dielectric layer located between the source and the gate, as well as between the drain and the gate;

wherein the source is electrically connected with the source area through a first through-hole passing through the interlayer dielectric layer and the gate insulating layer, and the drain is electrically connected with the drain area through a second through-hole passing through the interlayer dielectric layer and the gate insulating layer.

5. An array substrate, comprising the Thin Film Transistor according to claim 1.

6. The array substrate according to claim 5, further comprising a flat layer and a pixel electrode ordinally located above the Thin Film Transistor;

wherein the pixel electrode is electrically connected with the drain in the Thin Film Transistor through a contact hole.

7. A display device comprising the array substrate according to claim 5.

8. A method for manufacturing a Thin Film Transistor according to claim 1, comprising the steps of:

forming a pattern of an active layer, a source area electrically connected with a source to be formed and a drain area electrically connected with a drain to be formed simultaneously on the base substrate, wherein the source area and the drain area are oppositely arranged to each other;

forming a pattern of a gate insulating layer covering the active layer on a base substrate;

forming a conductive layer on the gate insulating layer;

forming a pattern of a gate on the conductive layer, wherein an offset area is in a channel between the gate and the active layer; and

processing the conductive layer by a patterning process and forming a pattern of the conductive layer, so that there is the conductive layer in the offset area, a projection of the gate on the base substrate, a projection of the conductive layer on the base substrate and a projection of the active layer on the base substrate partially overlap with one another, the projection of the conductive layer on the base substrate is larger than the projection of the gate on the base substrate, and the projection of the active layer on the base substrate is larger than the projection of the conductive layer on the base substrate.

9. The method according to claim 8, wherein the step of processing the conductive layer by a patterning process and forming a pattern of the conductive layer comprises the step of:

plasma bombarding the conductive layer by a plasma process so that the projection of the pattern of the conductive layer on the base substrate is greater than the projection of the gate on the base substrate.

10. The method according to claim 8, further comprising the step of forming a pattern of the source and that of the drain after the step of forming a pattern of the gate.

11. The method according to claim 10, wherein after the step of forming a pattern of the gate and before the step of forming a pattern of the source and that of the drain, the method further comprises the steps of:

forming an interlayer dielectric layer covering the gate; and

forming a first through-hole and a second through-hole passing through the interlayer dielectric layer and the gate insulating layer, the first through-hole used for electrically connecting the source to be formed with the source area, and the second through-hole for electrically connecting the drain to be formed with the drain area.

12. The method according to claim 8, wherein the conductive layer is made of one or more materials of a carbon material, metallic material and metallic oxide which are conductive.