Systems and methods for utilizing DDR4-DRAM chips in hybrid DDR5-DIMMs and for cascading DDR5-DIMMs

• US 10,628,343 B2
• Filed: 02/03/2017
• Issued: 04/21/2020
• Est. Priority Date: 02/03/2017
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Lee, Xiaobing
• Primary Examiner(s): Oberly, Eric T
• Application Number:
  US15/424,638
• Publication Number:
  US 20180225235A1
• Time in Patent Office: 1,173 Days
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

A hybrid DDR5 DIMM device includes a PCB board with a host interface through one of two DDR5 sub-channels, and a plurality of DDR4 or slow DDR5 SDRAM chips on the PCB coupled to this single channel DDR5 host interface. An embodiment processing system includes a host CPU to access one or more pairs of hybrid DDR5 DIMM devices for 4×DDR5 memory capacities (4DPC), a first or second hybrid DDR5 DIMM including a plurality of half-speed SDRAM chips, and a first or second DDR5 sub-channel coupled the host with slow SRAM chips on DIMM. Mounting same data-buffer and RCD chips on hybrid DIMM to a server motherboard can double available DDR4 DIMMs'"'"' speed to DDR5 speed rate. Pairs of hybrid DDR5 DIMM devices cascaded one-by-one can aggregate more DDR5 DIMM devices to expand memory capacities at double speed of DDR4 or DDR5 SDRAM chips, beyond current DDR5 speed limit 6400 MT/s.

Claims

1. A hybrid double data rate 5 (DDR5) dual inline memory module (DIMM) comprising:

a printed circuit board (PCB);

an edge connector of the PCB comprising a solitary DIMM external host interface, wherein the solitary DIMM external host interface is for only one DDR5 sub-channel;

a plurality of DDR4 synchronous dynamic random access memory (SDRAM) chips mounted on the PCB and operatively coupled to the solitary DIMM external host interface; and

a plurality of data-buffer chips and a registered clock driver (RCD) chip mounted on the PCB.

2. The hybrid DDR5 DIMM of claim 1, further comprising each of the plurality of data-buffer chips operatively coupled between the solitary DIMM external host interface and two subsets of the plurality of DDR4 SDRAM chips as a 1-to-2 byte-channel splitting and speed-rate doubling application-specific integrated circuit (ASIC) chip to fan-out to the two subsets of the plurality of DDR4 SDRAM chips.

3. The hybrid DDR5 DIMM of claim 2, wherein the one DDR5 sub-channel at each data-buffer chip has a first host interface rate, and wherein DDR4 byte-channels between each data-buffer chip and respective subsets of the plurality of DDR4 SDRAM chips each has a second memory interface rate that is half of the first host interface rate.

4. The hybrid DDR5 DIMM of claim 2, further comprising the RCD chip operatively coupled between the solitary DIMM external interface and the plurality of DDR4 SDRAM chips, as a DDR5-to-DDR4 command and address adaptor.

5. The hybrid DDR5 DIMM of claim 1,

wherein the one DDR5 sub-channel comprises four host data bytes and one error correcting code (ECC) byte;

and

wherein the plurality of DDR4 SDRAM chips is 18 DDR4 SDRAM chips or 36 DDR4 SDRAM chips, with two or four DDR4 SDRAM chips for ECC, respectively.

6. The hybrid DDR5 DIMM of claim 5, further comprising:

four data data-buffers chips, each data-buffer chip coupled between a respective one of the four host data bytes and a respective subset of eight DDR4 byte-channels then the plurality of DDR4 SDRAM chips, and one data-buffer chip for a ECC byte-channel, to fit 4-bytes data and 1-byte ECC host interface into 8-bytes data and 1-byte ECC memory interface, wherein a speed rate of each DDR4 byte-channel is half of a speed rate of the solitary DIMM external host interface.

7. A processing system comprising:

a host central processing unit (CPU);

one or more pairs of hybrid double data rate 5 (DDR5) dual inline memory modules (DIMMs) configured as;

a first hybrid DDR5-DIMM comprising a first plurality of DDR4 SDRAM chips;

a second hybrid DDR5 DIMM comprising a second plurality of DDR4 SDRAM chips;

a solitary first memory channel coupled between the host CPU and the first hybrid DDR5 DIMM, the solitary first memory channel being a first DDR5 sub-channel; and

a solitary second memory channel coupled between the host CPU and the second hybrid DDR5 DIMM, the solitary second memory channel being a second DDR5 sub-channel; and

a motherboard interconnecting the host CPU with one pair of the hybrid DDR5 DIMMs at high speed, or two pairs of the hybrid DDR5 DIMMs at slow speed to access 4×

memory capacities.

8. The processing system of claim 7,

wherein the first DDR5 sub-channel comprises first 32-bits of data and first 8-bits of error correcting code (ECC);

and

wherein the second DDR5 sub-channel comprises second 32-bits of data and second 8-bits of ECC.

9. The processing system of claim 7, further comprising a DDR5 command and address interface from the host CPU to drive the one or more pairs of hybrid DDR5 DIMMs, as the first hybrid DDR5 DIMM and the second hybrid DDR5 DIMM.

10. The processing system of claim 7, further comprising:

a first group of four hybrid DDR5 DIMMs, including the first hybrid DDR5 DIMM, coupled in parallel to the first DDR5 sub-channel; and

a second group of four hybrid DDR5 DIMMs, including the second hybrid DDR5 DIMM, coupled in parallel to the second DDR5 sub-channel.

11. The processing system of claim 7, wherein each of the first and second DDR5 sub-channels is a greater than 4400 MT/s channel for accessing one pair of the hybrid DDR5 DIMMs, or slower for accessing two pairs of the hybrid DDR5 DIMMs as 4DPC capacities.

12. The processing system of claim 7, wherein each of the first and second hybrid DDR5 DIMMs supports 18 or 36 DDR4 SDRAM chips in a currently-available DDR4 DIMM form factor.

13. A method of operating a memory system, the method comprising:

receiving, by a hybrid double data rate 5 (DDR5)-dual inline memory module (DIMM), data via a solitary external memory channel for the hybrid DDR5-DIMM, the solitary external memory channel being an external DDR5 sub-channel;

splitting, on the hybrid DDR5-DIMM, the received data onto a plurality of pairs of DDR4 byte-channels; and

for each of the DDR4 byte-channels, storing the split data in a set of DDR4 synchronous dynamic random access memory (SDRAM) chips on the hybrid DDR5-DIMM.

14. The method of claim 13, wherein, for each pair of DDR4 byte-channels, the splitting further comprises interleaving the split data between two DDR4 byte-channels in the pair of DDR4 byte-channels.

15. The method of claim 14, wherein each set of DDR4 SDRAM chips comprises four DDR4 SDRAM chips, and wherein the storing further comprises accessing the DDR4 SDRAM chips as a four-rank memory.

16. The method of claim 13, further comprising:

operating the external DDR5 sub-channel at a first transaction rate; and

operating each of the DDR4 byte-channels at a second transaction rate that is half of the first transaction rate.

17. The method of claim 16, wherein the first transaction rate is 6400 mega-transactions per second (MT/s), and the second transaction rate is 3200 MT/s.

18. The method of claim 13, wherein the external DDR5 sub-channel comprises four data bytes, and wherein the splitting is performed by four data-buffers on the hybrid DDR5-DIMM, each data-buffer coupled between a respective data byte of the external DDR5 sub-channel and a respective pair of the DDR4 byte-channels.

19. The method of claim 13, further comprising:

receiving error correcting code (ECC) data via the external DDR5 sub-channel;

splitting, by an ECC data-buffer on the hybrid DDR5-DIMM, the ECC data to a pair of ECC DDR4 ports;

driving the split ECC data from one of the ECC DDR4 ports on an ECC DDR4 byte-channel; and

storing the split ECC data in another set of DDR4 SDRAM chips on the hybrid DDR5-DIMM.

20. The method of claim 13, further comprising:

receiving DDR5 commands and addresses via an external DDR5 control-channel;

latching, by a register clock driver (RCD) on the hybrid DDR5-DIMM, the DDR5 commands and addresses;

converting, by the RCD, the latched DDR5 commands and addresses into DDR4 SDRAM commands and addresses; and

providing the DDR4 SDRAM commands and addresses to all of the DDR4 SDRAM chips via a single data rate (SDR) control bus operating at half of an SDR speed of the external DDR5 control-channel.

21. A method of cascading a double data rate 5 (DDR5) dual-channel system, the method comprising:

transferring first data via a first DDR5 sub-channel at a first host interface rate to a first hybrid DDR5 dual inline memory module (DIMM) comprising a first plurality of DDR4 synchronous dynamic random access memory (SDRAM) chips and only one first external memory channel interface, the first external memory channel interface being a first DDR5 sub-channel interface; and

transferring second data via a second DDR5 sub-channel at the first host interface rate to a second hybrid DDR5 DIMM comprising a second plurality of DDR4 SDRAM chips and only one second external memory channel interface, the second external memory channel interface being a second external DDR5 sub-channel interface.

22. The method of claim 21, further comprising, on each of the first and second hybrid DDR5 DIMMS:

receiving the first or second data, respectively;

splitting the received first or second data onto a plurality of pairs of byte-channels having a slow second memory interface rate; and

for each of the byte-channels, storing the split first or second data in a respective subset of the DDR4 SDRAM chips.

23. The method of claim 22, wherein the splitting further comprises, for each pair of byte-channels, interleaving the split first or second data between two byte-channels depending on a falling edge or a rising edge of DQS strobe signals.

24. The method of claim 22, wherein the slow second memory interface rate is half of the first host interface rate for driving up to 4 slow SDRAM chips.

25. The method of claim 22, wherein the storing further comprises accessing the respective subset of the DDR4 SDRAM chips as a four-rank DIMM device.

26. The method of claim 22, further comprising:

transferring third data via the first DDR5 sub-channel at the first host interface rate to a third hybrid DDR5 DIMM comprising a third plurality of DDR4 SDRAM chips; and

transferring fourth data via the second DDR5 sub-channel at the first host interface rate to a fourth hybrid DDR5 DIMM comprising a fourth plurality of DDR4 SDRAM chips, through unused DDR5 sub-channels as cascading ports of cascading-switched data buffer chips.

27. The method of claim 26, wherein the first host interface rate is 6400 mega-transactions per second (MT/s) and the slow second memory interface rate is 3200 MT/s to access the DDR4 SDRAM chips for doubling DDR4 speed.

28. The method of claim 21, further comprising:

transferring first error correcting code (ECC) data via the first DDR5 sub-channel at the first host interface rate to the first hybrid DDR5 DIMM; and

transferring second ECC data via the second DDR5 sub-channel at the first host interface rate to the second hybrid DDR5 DIMM.

29. The method of claim 21, further comprising:

sending first DDR5 commands and addresses via the first DDR5 sub-channel to the first hybrid DDR5 DIMM; and

sending second DDR5 commands and addresses via the second DDR5 sub-channel to the second hybrid DDR5 DIMM.

30. The method of claim 29, further comprising:

converting, by a first register clock driver (RCD) on the first hybrid DDR5 DIMM, the first DDR5 commands and addresses to first DDR4 SDRAM commands and addresses;

providing the first DDR4 SDRAM commands and addresses to the first plurality of DDR4 SDRAM chips;

converting, by a second RCD on the second hybrid DDR5 DIMM, the second DDR5 commands and addresses to second DDR4 SDRAM commands and addresses;

providing the second DDR4 SDRAM commands and addresses to the second plurality of DDR4 SDRAM chips; and

regenerating consecutive DDR4 burst access command addresses to adapt DDR5 burst 32 (BL32) as two DDR4 bursts (2 BL8) cross-bank or cross-rank accesses.