Power integrated module

• US 10,629,550 B2
• Filed: 01/20/2017
• Issued: 04/21/2020
• Est. Priority Date: 10/31/2012
• Status: Active Grant

• Current Assignee: Delta Electronics Company Limited (Delta Electronics Incorporated)
• Original Assignee: Delta Electronics Company Limited (Delta Electronics Incorporated)
• Inventors: Zeng, Jianhong, Chen, Yan, Liang, Le, Xin, Xiaoni
• Primary Examiner(s): Ahmed, Selim U
• Application Number:
  US15/410,858
• Publication Number:
  US 20170133332A1
• Time in Patent Office: 1,187 Days
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6661 for passive devices passive components per se H01L28/00
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/08195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/08265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24245 the item being metallic
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/04 : Structure, shape, material or disposition of the bonding areas prior to the connecting process
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 27/0203 : Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and including a first, a second and a control end; a first electrode, connected to the first end of the first upper bridge switch; a second electrode, connected to the second end of the first lower bridge switch; and a third electrode, connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch, wherein the first, the second and the third electrode are bar-type electrodes arranged side by side.

Claims

1. A power integrated module, comprising at least one first bridge formed in a chip, a first bus terminal, a second bus terminal and a third bus terminal, wherein the first bridge comprises:

a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

a first electrode, electrically connected to the first end of the first upper bridge switch;

a second electrode, electrically connected to the second end of the first lower bridge switch; and

a third electrode, electrically connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch,

wherein the first bus terminal is electrically connected to the first electrode, the second bus terminal is electrically connected to the second electrode, and the third bus terminal is electrically connected to the third electrode,

the first electrode, the second electrode and the third electrode are bar-type electrodes arranged side by side, and located above the first upper bridge switch and the first lower bridge switch, and

the first bus terminal, the second bus terminal and the third bus terminal are distributed in a bus area, the bus area contains a first bus area, a second bus area and a third bus area arranged side by side, projections of the first bus area, the second bus area and the third bus area with respect to the chip intersect with and at least partly overlap with the first electrode, the second electrode and the third electrode, and projections of the first bus area, the second bus area and the third bus area with respect to the chip at least partly overlap with the chip, and

wherein the first bus terminal comprises a plurality of segments of first sub bus terminals, the second bus terminal comprises a plurality of segments of second sub bus terminals, a part of the plurality of segments of first sub bus terminals and a part of the plurality of segments of second sub bus terminals are interleaved in the first bus area, another part of the plurality of segments of first sub bus terminals and another part of the plurality of segments of second sub bus terminals are interleaved in the second bus area, and the third bus terminal is a bar-type electrode and located in the third bus area.

2. The power integrated module according to claim 1, wherein the first electrode, the second electrode and the third electrode are parallel to each other, the first bus area, the second bus area and the third bus area are parallel to each other, and the first bus area, the second bus area and the third bus area are perpendicular to the first electrode, the second electrode and the third electrode.

3. The power integrated module according to claim 1, wherein the first bus terminal, the second bus terminal and the third bus terminal are bar-type electrodes, and the first bus terminal, the second bus terminal and the third bus terminal are arranged in parallel and side by side.

4. The power integrated module according to claim 1, wherein he third bus area is located between the first bus area and the second bus area.

5. The power integrated module according to claim 1, wherein

an insulating layer is provided between the first bus terminal, the second bus terminal and the third bus terminal and the first electrode, the second electrode and the third electrode, and

the first bus terminal, the second bus terminal and the third bus terminal are electrically connected to the first electrode, the second electrode and the third electrode through holes.

6. The power integrated module according to claim 1, wherein the power integrated module further comprises at least one second bridge formed in the chip, and the second bridge comprises:

a second upper bridge switch, formed by a plurality of third sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

a second lower bridge switch, formed by a plurality of fourth sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

a fourth electrode, electrically connected to the first end of the second upper bridge switch;

a fifth electrode, electrically connected to the second end of the second lower bridge switch; and

a sixth electrode, electrically connected to the second end of the second upper bridge switch and the first end of the second lower bridge switch.

7. The power integrated module according to claim 6, wherein the first bus terminal comprises a plurality of segments of first sub bus terminals, the second bus terminal comprises a plurality of segments of second sub bus terminals, the plurality of segments of first sub bus terminals and the plurality of segments of second sub bus terminals are interleaved in the first bus area and the second bus area, the third bus terminal is a bar-type electrode and located in the third bus area, the power integrated module further contains a fourth bus terminal, the fourth bus terminal is electrically connected to the sixth electrode and located in the third bus area, and the fourth bus terminal and the third bus terminal are arranged side by side.

8. The power integrated module according to claim 1, further comprising:

at least one driving circuit, configured to generate a driving signal and correspondingly output the driving signal to the control end of the upper bridge switch and the control end of the lower bridge switch,

wherein the driving circuit is formed in a bar-type region in the chip, and the bar-type region is arranged close to the first upper bridge switch and the first lower bridge switch.

9. The power integrated module according to claim 1, further comprising:

at least two bus capacitors, electrically connected to the first electrode and the second electrode.

10. The power integrated module according to claim 9, wherein the power integrated module is provided on a carrier plate, the bus capacitors are provided at two ends of the first electrode and the second electrode respectively, and a projection of the chip with respect to the carrier plate does not overlap a projection of the bus capacitor with respect to the carrier plate.

11. The power integrated module according to claim 9, wherein the bus capacitors are provided above the chip.

12. A power integrated module, comprising at least one bridge and a plurality of driving circuits formed in a chip, wherein the bridge comprises:

an upper bridge switch, formed by a plurality of first sub switches connected in parallel, and comprising a first end, a second end and a control end;

a lower bridge switch, formed by a plurality of second sub switches connected in parallel, and comprising a first end, a second end and a control end;

a first electrode, electrically connected to the first end of the upper bridge switch;

a second electrode, electrically connected to the second end of the lower bridge switch; and

a third electrode, electrically connected to the second end of the upper bridge switch and the first end of the lower bridge switch,

wherein the respective driving circuits are configured to generate a driving signal based on a control signal, and correspondingly output the driving signal to the control end of the upper bridge switch and the control end of the lower bridge switch, and

the first electrode, the second electrode and the third electrode are bar-type electrodes arranged side by side and located above the chip, the driving circuit is formed in a bar-type region in the chip, and the bar-type region is arranged close to the upper bridge switch and the lower bridge switch.

13. The power integrated module according to claim 12, wherein the third electrode of the bridge is located between the first electrode and the second electrode.

14. The power integrated module according to claim 13, wherein

the chip comprises a first region and a second region which are adjacent to each other, and the first region is configured to provide the control signal, and

the driving circuit, the first electrode, the second electrode and the third electrode are located in the second region.

15. The power integrated module according to claim 13, wherein more than one bridge is formed in the chip, and the first electrodes, the second electrodes and the third electrodes of the bridges are arranged side by side.

16. The power integrated module according to claim 15, wherein two adjacent bridges share one of the first electrodes or share one of the second electrodes.

17. The power integrated module according to claim 15, wherein the first electrodes of the bridges are electrically connected to each other, the second electrodes of the bridges are electrically connected to each other, and the third electrodes of the bridges are electrically connected to each other.

18. The power integrated module according to claim 15, wherein each bridge further comprises:

a fourth electrode, electrically connected to the second end of the upper bridge switch and the first end of the lower bridge switch; and

a fifth electrode, electrically connected to the first end of the upper bridge switch, wherein the fourth electrode is located between the fifth electrode and the second electrode, or

a fifth electrode, electrically connected to the second end of the lower bridge switch, wherein the fourth electrode is located between the fifth electrode and the first electrode.

19. A power integrated module, comprising at least one first bridge formed in a chip, a first bus terminal, a second bus terminal and a third bus terminal, wherein the first bridge comprises:

a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and comprising a first end, a second end and control end;

a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

a first electrode, electrically connected to the first end of the first upper bridge switch;

a second electrode, electrically connected to the second end of the first lower bridge switch; and

a third electrode, electrically connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch,

wherein the first bus terminal is electrically connected to the first electrode, the second bus terminal is electrically connected to the second electrode, and the third bus terminal is electrically connected to the third electrode,

the first electrode, the second electrode and the third electrode are bar-type electrodes located above the first upper bridge switch and the first lower bridge switch, and

the first bus terminal, the second electrode terminal and the third bus terminal are distributed in a bus area, the bus area contains a first bus area, a second bus area and a third bus area, projections of the first bus area, the second bus area and the third bus area with respect to the chip intersect with and at least partly overlap with the first electrode, the second electrode and the third electrode, and projections of the first bus area, the second bus area and the third bus area with respect to the chip at least partly overlap with the chip; and

the power integrated module further comprises at least one second bridge formed in the chip, and the second bridge comprises;

a second upper bridge switch, formed by a plurality of third sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

a second lower bridge switch, formed by a plurality of fourth sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

a fourth electrode, electrically connected to the first end of the second upper bridge switch;

a fifth electrode, electrically connected to the second end of the second lower bridge switch; and

a sixth electrode, electrically connected to the second end of the second upper bridge switch and the first end of the second lower bride switch, and

the sixth electrode is located between the fourth electrode and the second electrode, and the sixth electrode is beside the fourth electrode and the second electrode, or

the sixth electrode is located between the filth electrode and the first electrode, and the sixth electrode is beside the fifth electrode and the first electrode.

20. The power integrated module according to claim 19, wherein the third electrode is located between the first electrode and the second electrode and the third electrode is beside the first electrode and the second electrode, the first end of the second upper bridge switch is electrically connected to the first end of the first upper bridge switch, the second end of the second upper bridge switch is electrically connected to the second end of the first upper bridge switch, and the second end of the second lower bridge switch electrically is connected to the second end of the first lower bridge switch.

21. The power integrated module according to claim 19, wherein

the first electrode and the fourth electrode are merged into one merged electrode, and the first to sixth electrodes are arranged side by side in an order of arrangement of the second electrode, the third electrode, the merged electrode, the sixth electrode and the fifth electrode, or

the second electrode and the fifth electrode are merged into one merged electrode, and the first to sixth electrodes are arranged side by side in an order of arrangement of the first electrode, the third electrode, the merged electrode, the sixth electrode and the fourth electrode.

22. The power integrated module according to claim 19, further comprising:

at least one driving circuit, configured to generate a driving signal and correspondingly output, the driving signal to the control end of the upper bridge switch and the control end of the lower bridge switch,

wherein the driving circuit is formed in a bar-type region in the chip, and the bar-type region is arranged close to the first upper bridge switch and the first lower bridge switch.

23. The power integrated module according to claim 19, further comprising:

at least two bus capacitors, electrically connected to the first electrode and the second electrode.

24. The power integrated module according to claim 23, wherein the power integrated module is provided on a carrier plate, the bus capacitors are provided at two ends of the first electrode and the second electrode respectively, and a projection of the chip with respect to the carrier plate does not overlap a projection of the bus capacitor with respect to the carrier plate.

25. The power integrated module according to claim 23, wherein the bus capacitors are provided above the chip.