Power integrated module

  • US 10,629,550 B2
  • Filed: 01/20/2017
  • Issued: 04/21/2020
  • Est. Priority Date: 10/31/2012
  • Status: Active Grant
First Claim
Patent Images

1. A power integrated module, comprising at least one first bridge formed in a chip, a first bus terminal, a second bus terminal and a third bus terminal, wherein the first bridge comprises:

  • a first upper bridge switch, formed by a plurality of first sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

    a first lower bridge switch, formed by a plurality of second sub switches formed in the chip connected in parallel, and comprising a first end, a second end and a control end;

    a first electrode, electrically connected to the first end of the first upper bridge switch;

    a second electrode, electrically connected to the second end of the first lower bridge switch; and

    a third electrode, electrically connected to the second end of the first upper bridge switch and the first end of the first lower bridge switch,wherein the first bus terminal is electrically connected to the first electrode, the second bus terminal is electrically connected to the second electrode, and the third bus terminal is electrically connected to the third electrode,the first electrode, the second electrode and the third electrode are bar-type electrodes arranged side by side, and located above the first upper bridge switch and the first lower bridge switch, andthe first bus terminal, the second bus terminal and the third bus terminal are distributed in a bus area, the bus area contains a first bus area, a second bus area and a third bus area arranged side by side, projections of the first bus area, the second bus area and the third bus area with respect to the chip intersect with and at least partly overlap with the first electrode, the second electrode and the third electrode, and projections of the first bus area, the second bus area and the third bus area with respect to the chip at least partly overlap with the chip, andwherein the first bus terminal comprises a plurality of segments of first sub bus terminals, the second bus terminal comprises a plurality of segments of second sub bus terminals, a part of the plurality of segments of first sub bus terminals and a part of the plurality of segments of second sub bus terminals are interleaved in the first bus area, another part of the plurality of segments of first sub bus terminals and another part of the plurality of segments of second sub bus terminals are interleaved in the second bus area, and the third bus terminal is a bar-type electrode and located in the third bus area.

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