Negatively sloped isolation structures

• US 10,636,695 B2
• Filed: 09/11/2019
• Issued: 04/28/2020
• Est. Priority Date: 06/15/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Singh, Gulbagh, Tsai, Tsung-Han, Chuang, Kun-Tsang
• Primary Examiner(s): Vu, Hung K
• Application Number:
  US16/567,860
• Publication Number:
  US 20200006114A1
• Time in Patent Office: 230 Days
• Field of Search: None
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Negatively sloped isolation structures are formed on a semiconductor substrate to isolate devices from one another. The negatively sloped isolation structures have a top critical dimension which is smaller than a bottom critical dimension. The negatively sloped isolation structures may penetrate through an insulator layer of a silicon-on-insulator structure arrangement.

Claims

1. A structure comprising:

a semiconductor material layer;

a first isolation structure embedded in the semiconductor material layer;

a second isolation structure embedded in the semiconductor material layer, wherein the first isolation structure and second isolation structure each have a top width and a bottom width, wherein the bottom width is greater than the top width;

a third isolation structure embedded in the semiconductor material layer, the third isolation structure having a top width and a bottom width, wherein the top width of the third isolation structure is greater than the bottom width of the third isolation structure; and

a device region of the semiconductor material layer disposed between the first isolation structure and the second isolation structure, wherein the device region has a device formed therein.

2. The structure of claim 1, further comprising:

an insulator layer underlying the semiconductor material layer, wherein the first isolation structure extends below the semiconductor material layer into the insulator layer.

3. The structure of claim 2, wherein the first isolation structure extends completely through the insulator layer.

4. The structure of claim 3, further comprising:

a substrate underlying the insulator layer, wherein the first isolation structure extends into the substrate.

5. The structure of claim 3, further comprising:

an air gap embedded in the first isolation structure.

6. The structure of claim 1, wherein the first isolations structure includes an air gap embedded therein, and wherein the third isolation structure comprises a solid material throughout its entirety.

7. The structure of claim 1, wherein the first isolation structure and the second isolation structure merge together at an end of the device region.

8. The structure of claim 1, wherein an upper surface of the first isolation structure and the second isolation structure extend vertically higher than an upper surface of the semiconductor material layer.

9. A device comprising:

an insulating layer disposed over a substrate;

a semiconductor layer disposed over the insulating layer;

a first isolation structure and a second isolation structure embedded in the semiconductor layer, each of the first isolation structure and the second isolation structure extending into the insulating layer, each of the first isolation structure and the second isolation structure having angled sidewalls, wherein a first angle between an upper surface of the first isolation structure and a first adjoining sidewall of the first isolation structure is less than 90 degrees;

a third isolation structure embedded in the semiconductor layer, the third isolation structure having a top surface level with a top surface of the first isolation structure, the third isolation structure having a height less than a height of the first isolation structure; and

a device region disposed between the first isolation structure and the second isolation structure.

10. The device of claim 9, wherein the first isolation structure and the second isolation structure extend completely through the insulating layer.

11. The device of claim 10, wherein the first isolation structure and the second isolation structure have a bottom surface embedded in the substrate.

12. The device of claim 10, wherein the first isolation structure and the second isolation structure each have an air gap embedded therein.

13. The device of claim 9, wherein the third isolation structure has angled sidewalls, wherein a second angle between an lower surface of the third isolation structure and a second adjoining sidewall of the third isolation structure is less than 90 degrees.

14. The device of claim 9, wherein the device region comprises a radio frequency (RF) device.

15. A device comprising:

a film stack comprising an insulator layer disposed over a substrate and a semiconductor layer disposed over the insulator layer;

a first set of isolation structures embedded in the film stack, the first set of isolation structures each having non-vertical sidewalls, an upper surface, and a bottom surface, wherein a first width of the upper surface is greater than a second width of the bottom surface;

a second set of isolation structures embedded in the film stack, the second set of isolation structures each having non-vertical sidewalls, an upper surface, and a bottom surface, wherein for each isolation structure in the second set of isolation structures, a third width of the upper surface is less than a fourth width of the bottom surface; and

a device region of the semiconductor layer laterally surrounded by the first set of isolation structures.

16. The device of claim 15, further comprising:

a third set of isolation structures embedded in the film stack, the third set of isolation structures each having non-vertical sidewalls, the third set of isolation structures each extending completely through the insulator layer, the third set of isolation structures each having an air gap embedded therein.

17. The device of claim 15, wherein, for each isolation structure in the first set of isolation structures, a ratio of a height of each to a width of each is between 0.5 and 10.

18. The device of claim 15, wherein the ratio is between 4 and 10.

19. The device of claim 15, wherein the upper surface of the each of the first set of isolation structures and the upper surface of each of the second set of isolation structures extend vertically higher than an upper surface of the semiconductor layer.

20. The device of claim 15, wherein the bottom surface of each of the first set of isolation structures extends into the insulator layer below the semiconductor layer.