Apparatus and method to prevent integrated circuit from entering latch-up mode
First Claim
1. An apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode, the apparatus comprising:
- a p-type substrate;
an n-well within the p-type substrate;
an n-type region within the p-type substrate, the n-type region being distinct from the n-well;
a p-type region within the n-well, wherein the n-well is free of n-type regions therein;
a power supply electrically coupled to the p-type region within the n-well; and
a directional diode directly electrically coupling the power supply to a metal contact within the n-well in parallel with the p-type region, wherein the directional diode biases a current flow from the power supply to the n-well, and wherein the directional diode contacts the n-well distal to the p-type region.
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Accused Products
Abstract
The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.
35 Citations
20 Claims
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1. An apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode, the apparatus comprising:
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a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well, wherein the n-well is free of n-type regions therein; a power supply electrically coupled to the p-type region within the n-well; and a directional diode directly electrically coupling the power supply to a metal contact within the n-well in parallel with the p-type region, wherein the directional diode biases a current flow from the power supply to the n-well, and wherein the directional diode contacts the n-well distal to the p-type region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode, the apparatus comprising:
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a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well, wherein the n-type region is electrically coupled to ground; a p-type region within the n-well, wherein the n-well is free of n-type regions therein; and a directional diode directly electrically coupling a metal contact within the p-type substrate to ground in parallel with the n-type region, wherein the directional diode biases a current flow from the p-type substrate to ground, and wherein the directional diode contacts the p-type substrate distal to the n-type region. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode, the apparatus comprising:
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a p-type substrate; an n-well within the p-type substrate; a first device formed over the p-type substrate, and a pair of n-type terminals within the p-type substrate, wherein the p-type substrate is free of p-type regions therein; a second device formed over the n-well, and a pair of p-type terminals within the n-well, wherein the n-well is free of n-type regions therein; a first shallow trench isolation (STI) on the p-type substrate and the n-well, and between the first and second devices; a power supply electrically coupled to one of the pair of p-type terminals of the second device; a directional diode electrically directly coupling the power supply to a metal contact within the n-well in parallel with the one of the pair of p-type terminals of the second device, wherein the directional diode biases a current flow from the power supply to the n-well, and wherein the directional diode contacts the n-well distal to the second device; and a second shallow trench isolation (STI) over the n-well between the second transistor and the directional diode. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification