Semiconductor device

• US 10,643,960 B2
• Filed: 11/15/2018
• Issued: 05/05/2020
• Est. Priority Date: 12/25/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kariyazaki, Shuuichi, Shiroi, Wataru, Katayama, Shinji, Tsuchiya, Keita
• Primary Examiner(s): Kim, Tong-Ho
• Application Number:
  US16/192,323
• Publication Number:
  US 20190198463A1
• Time in Patent Office: 537 Days
• Field of Search: 257668
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6638 Differential pair signal lines
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.

Claims

1. A semiconductor device, comprising:

a semiconductor chip including a first surface, a second surface opposite to the first surface, a first side, a second side opposite the first side, a first electrode formed on the first surface and a second electrode formed on the first surface; and

a wiring substrate including a first main surface over which the semiconductor chip is mounted, a second main surface opposite to the first main surface, a first wire for output signals extending in a first direction along the first main surface and located between the first main surface and the second main surface, a second wire for input signals extending in the first direction and located closer to the first main surface than the first wire in a cross-section view,

wherein the first wire is electrically connected with the first electrode of the semiconductor chip,

wherein the second wire is electrically connected with the second electrode of the semiconductor chip and is located between a first conductor pattern and a second conductor pattern in a cross-section view, and

wherein, when a cross-sectional area of each of the first wire and the second wire is defined as a wire cross-sectional area in a second direction orthogonal to the first direction, the wire cross-sectional area of the second wire is smaller than the wire cross-sectional area of the first wire.

2. The semiconductor device according to claim 1,

wherein the first conductor pattern is located between the first wire and the second wire in the cross-section view, and

wherein the second conductor pattern is located between the first main surface and the second wire in the cross-section view.

3. The semiconductor device according to claim 2,

wherein a third conductor pattern is located between the first main surface of the wiring substrate and the second conductor pattern.

4. The semiconductor device according to claim 3,

wherein the first and second conductor pattern are supplied with a reference potential, and

wherein the third conductor pattern is supplied with a first potential.

5. The semiconductor device according to claim 4,

wherein the reference potential is a ground potential.

6. The semiconductor device according to claim 3,

wherein the first electrode of the semiconductor chip is located between a center portion of the first surface of the semiconductor chip and the first side of the semiconductor chip,

wherein the second electrode of the semiconductor chip is located between the first electrode of the semiconductor chip and the first side of the semiconductor chip.

7. The semiconductor device according to claim 6,

wherein the first surface of the semiconductor chip faces the first main surface of the wiring substrate, and

wherein a plurality of external electrodes is formed on the second main surface of the wiring substrate.

8. The semiconductor device according to claim 3,

wherein the semiconductor chip includes a third electrode for output signals formed on the first surface and a fourth electrode for input signals formed on the first surface,

wherein the wiring substrate includes a third wire for output signals formed in a first wiring layer in which the first wire is formed, and a fourth wire for input signals formed in a second wiring layer in which the second wire is formed,

wherein the third wire is electrically connected with the third electrode, and

wherein the fourth wire is electrically connected with the fourth electrode.

9. The semiconductor device according to claim 8,

wherein the first and third wires are located side by side, and

wherein the second and fourth wires are located side by side.

10. The semiconductor device according to claim 9,

wherein the third electrode of the semiconductor chip is located between a center portion of the first surface of the semiconductor chip and the first side of the semiconductor chip,

wherein the fourth electrode of the semiconductor chip is located between the third electrode of the semiconductor chip and the first side of the semiconductor chip.

11. The semiconductor device according to claim 10,

wherein a pair of the first and third electrodes is a first differential pair, and

wherein a pair of the second and fourth electrodes is a second differential pair.

12. The semiconductor device according to claim 9,

wherein a pair of the first and third wires is a first differential pair, and

wherein a pair of the second and fourth wires is a second differential pair.

13. The semiconductor device according to claim 12,

wherein, in the cross-section view, the second and fourth wires are sandwiched between the third conductor formed in the second wiring layer and a fourth conductor formed in the second wiring layer.

14. The semiconductor device according to claim 13,

wherein, in the cross-section view, each of the third and fourth conductors is electrically connected with the first conductor via a plurality of first through hole wires.

15. The semiconductor device according to claim 14,

wherein, in the cross-section view, each of the third and fourth conductors is electrically connected with the first conductor via a plurality of second through hole wires.

16. The semiconductor device according to claim 15,

wherein, in the cross-section view, the first and third wires are sandwiched between a fifth conductor formed in the first wiring layer and a sixth conductor formed in the first wiring layer.

17. The semiconductor device according to claim 16,

wherein, in the cross-section view, each of the fifth and sixth conductors is electrically connected with the first conductor via a plurality of third through hole wires.