Semiconductor device

• US 10,644,019 B2
• Filed: 04/26/2019
• Issued: 05/05/2020
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Yoo-cheol, Park, Young-woo, Lee, Jae-duk
• Primary Examiner(s): Bradford, Peter
• Application Number:
  US16/396,027
• Publication Number:
  US 20190252401A1
• Time in Patent Office: 375 Days
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Claims

1. A semiconductor device, comprising:

a first substrate including a first region and a second region;

a first lower interconnection structure on the first region of the first substrate;

a second lower interconnection structure on the second region of the first substrate;

a second substrate on or above the first lower interconnection structure;

a memory cell array on the second substrate;

a first vertical contact penetrating through the memory cell array and the second substrate, and contacting the first lower interconnection structure;

a second vertical contact contacting the second lower interconnection structure; and

a channel layer penetrating through the memory cell array and contacting the second substrate.

2. The semiconductor device of claim 1, further comprising:

at least one insulating layer on the first substrate; and

a second insulating layer on the at least one insulating layer,

wherein the first lower interconnection structure and the second lower interconnection structure are in the at least one insulating layer, and

the second vertical contact penetrates the second insulating layer.

3. The semiconductor device of claim 2, wherein the second substrate is on the at least one insulating layer.

4. The semiconductor device of claim 1, wherein the second substrate is directly above the first region of the first substrate and does not vertically overlap the second region of the first substrate.

5. The semiconductor device of claim 1, wherein the memory cell array is directly above the first region of the first substrate and does not vertically overlap the second region of the first substrate.

6. The semiconductor device of claim 1, further comprising an upper interconnection layer electrically connected to the first lower interconnection structure via the first vertical contact.

7. The semiconductor device of claim 1, wherein the second vertical contact does not contact the memory array and the second substrate.

8. The semiconductor device of claim 1, wherein the second vertical contact is directly above the second region of the first substrate.

9. The semiconductor device of claim 1, wherein the channel layer is U-shaped.

10. The semiconductor device of claim 9, further comprising a buried insulating layer filling an interior space of the U-shaped channel layer.

11. The semiconductor device of claim 1, wherein a bottom surface of the channel layer directly contacts an upper surface of the second substrate.

12. The semiconductor device of claim 1, wherein an upper surface of the second substrate has a recess at a contacting area where the channel layer contacts the second substrate.