Sub-pixel unit and method of controlling the same, pixel unit, array substrate, display device

• US 10,665,183 B2
• Filed: 07/20/2017
• Issued: 05/26/2020
• Est. Priority Date: 01/10/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Jiang, Liangliang, Gan, Quan
• Primary Examiner(s): Adediran, Abdul-Samad A
• Application Number:
  US15/757,286
• Publication Number:
  US 20180357968A1
• Time in Patent Office: 1,041 Days
• Field of Search: 345 92, 345690, 349114
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/133753 with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3637 with intermediate tones displayed by domain size control domain size control in flat matrix panels other than liquid crystal displays having memory effects G09G3/207
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Abstract

The present disclosure provides a sub-pixel unit and a method of controlling the same, a pixel unit, an array substrate, and a display device. In one embodiment, a sub-pixel unit includes: at least two subpixels. Each of the at least two subpixels includes: a first electrode; a second electrode; and a liquid crystal layer controlled by a voltage between the first electrode and the second electrode; at least one of the first electrode and the second electrode is a slit electrode. The two subpixels have different initial twist angles, and the initial twist angle is an included angle between a direction of a slit of the slit electrode and a direction where major axes of liquid crystal molecules are oriented when the liquid crystal layer is in an unpowered state, in the respective subpixel.

Claims

1. A pixel unit comprising several sub-pixel units, wherein:

at least one of the several sub-pixel units comprises at least two subpixels;

each of the at least two subpixels comprises;

a first electrode;

a second electrode; and

a liquid crystal layer controlled by a voltage between the first electrode and the second electrode;

at least one of the first electrode and the second electrode is a slit electrode;

the at least two subpixels have different initial twist angles, and each of the initial twist angles is an included angle between a direction of a slit of the slit electrode and a direction where major axes of liquid crystal molecules are oriented when the liquid crystal layer is in an unpowered state, in a corresponding subpixel of the at least two subpixels;

the several sub-pixel units comprise a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit;

the red sub-pixel unit comprises a first red subpixel and a second red subpixel having different initial twist angles;

the green sub-pixel unit comprises a first green subpixel and a second green subpixel having different initial twist angles;

the blue sub-pixel unit comprises;

a first blue subpixel and a second blue subpixel having different initial twist angles;

the first red subpixel, the first green subpixel and the first blue subpixel have a same initial twist angle of θ

₁; and

the second red subpixel, the second green subpixel and the second blue subpixel have a same initial twist angle of θ

₂.

2. The pixel unit of claim 1, wherein,

two subpixels of each of the sub-pixel units are arranged in a first direction;

and

the first subpixels or the second subpixels of different sub-pixel units are arranged sequentially in a second direction that is neither coincident with nor parallel to the first direction.

3. The pixel unit of claim 1, wherein,

two subpixels of each of the sub-pixel units are arranged in a first direction;

and

the first subpixels and the second subpixels of different sub-pixel units are arranged alternately in a second direction that is neither coincident with nor parallel to the first direction.

4. The pixel unit of claim 1, wherein,

two subpixels of each of the sub-pixel units are arranged in a first direction;

and

the first subpixels and the second subpixels of different sub-pixel units are arranged randomly in a second direction that is neither coincident with nor parallel to the first direction.

5. The pixel unit of claim 1, wherein, both the θ

₁ and the θ

₂ are less than 15°

.

6. The pixel unit of claim 5, wherein, the θ

₁ and the θ

₂ are two different angles selected from a group consisting of 5°

, 7°

, and 11°

.

7. An array substrate, comprising:

a base substrate; and

an array of pixel units, disposed on the base substrate and comprising a plurality of pixel units arranged in array, at least one pixel unit of the plurality of pixel units being the pixel unit of claim 1.

8. The array substrate of claim 7, further comprising:

gate lines and data lines formed on the base substrate;

wherein, in the at least one pixel unit, two subpixels of each of the sub-pixel units share a same gate line and are controlled by different data lines.

9. The array substrate of claim 7, wherein, in the at least one pixel unit:

two subpixels of each of the sub-pixel units are arranged in a first direction;

the first subpixels or the second subpixels of different sub-pixel units are arranged sequentially in a second direction that is neither coincident or nor parallel to the first direction; and

the array substrate further comprises gate lines and data lines formed on the base substrate;

wherein, the first direction is along a direction of the data lines and the second direction is along a direction of the gate lines.

10. The array substrate of claim 7, wherein, the array substrate is an array substrate with an IPS mode or an FFS mode;

wherein the sub-pixel units of the pixel unit each comprises;

a pixel electrode and a common electrode separated by an insulation layer;

the first electrode is one of the pixel electrode and the common electrode, and the second electrode is the other of the pixel electrode and the common electrode.

11. The array substrate of claim 7, wherein, in the at least one pixel unit,

two subpixels of each of the sub-pixel units are arranged in a first direction;

the first subpixels and the second subpixels of different sub-pixel units are arranged alternately in a second direction that is neither coincident with nor parallel to the first direction; and

the array substrate further comprises gate lines and data lines formed on the base substrate;

wherein, the first direction is along a direction of the data lines and the second direction is along a direction of the gate lines.

12. The array substrate of claim 7, wherein, in the at least one pixel unit,

two subpixels of each of the sub-pixel units are arranged in a first direction;

the first subpixels and the second subpixels of different sub-pixel units are arranged randomly in a second direction that is neither coincident with nor parallel to the first direction; and

the array substrate further comprises gate lines and data lines formed on the base substrate;

wherein, the first direction is along a direction of the data lines and the second direction is along a direction of the gate lines.

13. A display device, comprising:

the array substrate of claim 7.

14. The display device of claim 13, wherein,

the array substrate further comprises:

gate lines and data lines formed on the base substrate;

in the at least one pixel unit, two subpixels of each of the sub-pixel units share the same gate line and are controlled by different data lines.

15. The display device of claim 13, wherein,

the array substrate further comprises:

gate lines and data lines formed on the base substrate;

wherein, a first direction is along a direction of the data lines and a second direction is along a direction of the gate lines.

16. A method of controlling a sub-pixel unit, wherein the sub-pixel unit comprises at least two subpixels;

wherein, each of the at least two subpixels comprises;

a first electrode;

a second electrode; and

a liquid crystal layer controlled by a voltage between the first electrode and the second electrode;

at least one of the first electrode and the second electrode is a slit electrode; and

the at least two subpixels have different initial twist angles, and each of the initial twist angles is an included angle between a direction of a slit of the slit electrode and a direction where major axes of liquid crystal molecules are oriented when the liquid crystal layer is in an unpowered state, in a corresponding subpixel of the at least two subpixels, the method comprising;

a step A of, acquiring a display luminance value required by the sub-pixel unit; and

a step B of, selecting a corresponding working mode from a group of arrangements of the at least two subpixels, according to the sub-pixel unit required display luminance value,

wherein, the at least two subpixels comprise a first subpixel and a second subpixel, the first subpixel having an initial twist angle of θ

1, and the second subpixel having an initial twist angle of θ

2, wherein θ

1>

θ

2; and

wherein the step B comprises;

a sub-step B1 of, judging, if Δ

<

Δ

2, that the sub-pixel unit requires to display in a low luminance, and controlling only the first subpixel of the sub-pixel unit to work;

a sub-step B2 of, judging, if Δ

2≤

Δ

<

Δ

1, that the sub-pixel unit requires to display in a medium luminance, and controlling only the second subpixel of the sub-pixel unit to work; and

a sub-step B3 of, judging, if Δ

≥

Δ

1, that the sub-pixel unit requires to display in a high luminance, and controlling the first subpixel and the second subpixel of the sub-pixel unit to work simultaneously;

in which, Δ

is the display luminance value required by the sub-pixel unit, Δ

1 is a first luminance threshold of the sub-pixel unit, Δ

2 is a second luminance threshold of the sub-pixel unit, and Δ

1>

Δ

2.