Transistor and display device

• US 10,665,615 B2
• Filed: 09/12/2019
• Issued: 05/26/2020
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sasaki, Toshinari, Sakata, Junichiro, Tsubuku, Masashi
• Primary Examiner(s): Choi, Calvin Y
• Application Number:
  US16/569,070
• Publication Number:
  US 20200006393A1
• Time in Patent Office: 257 Days
• Field of Search: None
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Claims

1. A display device comprising a pixel, the pixel comprising:

a transistor comprising;

a gate electrode layer;

a first insulating layer over the gate electrode layer;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer comprising indium, gallium, and zinc;

a second insulating layer over the oxide semiconductor layer, the second insulating layer being in contact with a top surface and a side surface of a peripheral portion of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer over the second insulating layer, the source electrode layer and the drain electrode layer being electrically connected to the oxide semiconductor layer;

a third insulating layer over and in contact with a top surface of the oxide semiconductor layer, the third insulating layer overlapping with a channel formation region of the transistor;

a capacitor; and

a light-emitting element electrically connected to the transistor, the light-emitting element comprising;

a first electrode;

an EL layer over the first electrode; and

a second electrode over the EL layer,

wherein the second insulating layer is different from the third insulating layer, and

wherein the second insulating layer comprises a region overlapping with the capacitor.

2. The display device according to claim 1,

wherein the oxide semiconductor layer comprises a first region and a second region,

wherein the channel formation region is between the first region and the second region, and

wherein a carrier concentration of the first region is higher than a carrier concentration of the channel formation region.

3. A display device comprising a pixel, the pixel comprising:

a transistor comprising;

a gate electrode layer over and in direct contact with an insulating surface;

a first insulating layer over the gate electrode layer;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer comprising indium, gallium, and zinc;

a second insulating layer over the oxide semiconductor layer, the second insulating layer being in contact with a top surface and a side surface of a peripheral portion of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer over the second insulating layer, the source electrode layer and the drain electrode layer being electrically connected to the oxide semiconductor layer;

a third insulating layer over and in contact with a top surface of the oxide semiconductor layer, the third insulating layer overlapping with a channel formation region of the transistor;

a capacitor; and

a light-emitting element electrically connected to the transistor, the light-emitting element comprising;

a first electrode;

an EL layer over the first electrode; and

a second electrode over the EL layer,

wherein the second insulating layer is different from the third insulating layer,

wherein the second insulating layer comprises a region overlapping with the capacitor,

wherein one electrode of the capacitor is provided over and in direct contact with the insulating surface, and

wherein the one electrode of the capacitor comprises the same material as the gate electrode layer.

4. The display device according to claim 3,

wherein the oxide semiconductor layer comprises a first region and a second region,

wherein the channel formation region is between the first region and the second region, and

wherein a carrier concentration of the first region is higher than a carrier concentration of the channel formation region.

5. A display device comprising a pixel, the pixel comprising:

a transistor comprising;

a gate electrode layer;

a first insulating layer over the gate electrode layer;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer comprising indium, gallium, and zinc;

a second insulating layer over the oxide semiconductor layer, the second insulating layer being in contact with a top surface and a side surface of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer;

a third insulating layer over and in contact with a top surface of the oxide semiconductor layer, the third insulating layer overlapping with a channel formation region of the transistor;

a capacitor; and

a light-emitting element electrically connected to the transistor, the light-emitting element comprising;

a first electrode;

an EL layer over the first electrode; and

a second electrode over the EL layer,

wherein at least one of the source electrode layer and the drain electrode layer is provided over the second insulating layer,

wherein the second insulating layer is different from the third insulating layer, and

wherein the first insulating layer comprises a region overlapping with the capacitor.

6. The display device according to claim 5,

wherein the oxide semiconductor layer comprises a first region and a second region,

wherein the channel formation region is between the first region and the second region, and

wherein a carrier concentration of the first region is higher than a carrier concentration of the channel formation region.

7. A display device comprising a pixel, the pixel comprising:

a transistor comprising;

a gate electrode layer over and in direct contact with an insulating surface;

a first insulating layer over the gate electrode layer;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer comprising indium, gallium, and zinc;

a second insulating layer over the oxide semiconductor layer, the second insulating layer being in contact with a top surface and a side surface of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer;

a third insulating layer over and in contact with a top surface of the oxide semiconductor layer, the third insulating layer overlapping with a channel formation region of the transistor;

a capacitor; and

a light-emitting element electrically connected to the transistor, the light-emitting element comprising;

a first electrode;

an EL layer over the first electrode; and

a second electrode over the EL layer,

wherein at least one of the source electrode layer and the drain electrode layer is provided over the second insulating layer,

wherein the second insulating layer is different from the third insulating layer,

wherein the first insulating layer comprises a region overlapping with the capacitor,

wherein one electrode of the capacitor is provided over and in direct contact with the insulating surface, and

wherein the one electrode of the capacitor comprises the same material as the gate electrode layer.

8. The display device according to claim 7,

wherein the oxide semiconductor layer comprises a first region and a second region,

wherein the channel formation region is between the first region and the second region, and

wherein a carrier concentration of the first region is higher than a carrier concentration of the channel formation region.