Power sourcing equipment, and method and apparatus for power over Ethernet

• US 10,666,447 B2
• Filed: 10/12/2017
• Issued: 05/26/2020
• Est. Priority Date: 10/13/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: He, Ling
• Primary Examiner(s): Patel, Nitin C
• Assistant Examiner(s): Chang, Eric
• Application Number:
  US15/782,598
• Publication Number:
  US 20180109391A1
• Time in Patent Office: 957 Days
• CPC Class Codes: G05B 7/02 electric
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 12/40045 Details regarding the feeding of energy to the node from the bus

Abstract

An Ethernet power sourcing equipment (PSE), and a method and an apparatus for power over Ethernet (PoE), where the Ethernet PSE includes a PSE chip, a master control processor, a power supplying port, and a preprocessor. The preprocessor is configured to determine whether the master control processor starts upon power-on, control the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on, and control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD. Hence, the Ethernet PSE has abundant management functions and can quickly power on a PD.

Claims

1. A power sourcing equipment (PSE), comprising:

a PSE chip;

a master control processor coupled to the PSE chip, wherein the master control processor is configured to;

run BOOT of a basic input/output system (BIOS) during the master control processor starting upon power-on;

execute a main program during the master control processor starting upon power-on;

determine whether the PSE chip has supplied power to a powered device (PD) after completing the master control processor starting upon power-on;

obtain state information of the PSE chip when the PSE chip has supplied power to the PD;

use the state information as a start state for subsequently controlling the PSE chip; and

initialize the PSE chip when the PSE chip has not supplied power to the PD;

a power supplying port coupled to the PSE chip; and

a preprocessor coupled to the master control processor and the PSE chip, wherein the preprocessor is configured to perform the following during the master control processor starting upon power-on;

determine whether the master control processor starts upon power-on;

set the PSE chip to a manual mode;

control the PSE chip to detect whether the power supplying port is connected to a valid PD; and

control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD.

2. The PSE of claim 1, wherein the preprocessor is configured to:

obtain total output power for a plurality of PDs;

obtain agreed power of each of the PDs;

determine a to-be-powered-on PD according to the total output power and the agreed power of each of the PDs; and

control the PSE chip to power on the to-be-powered-on PD.

3. The PSE of claim 1, further comprising a master control chip, wherein the preprocessor and the master control processor are configured to run in the master control chip, and wherein the preprocessor is further configured to run before the master control processor loads the main program.

4. The PSE of claim 1, further comprising a master control chip, wherein the preprocessor and the master control processor are configured to run in the master control chip, and wherein the preprocessor is further configured to run before the master control processor skips to the main program.

5. The PSE of claim 1, further comprising a master control chip, and wherein the master control processor is configured to run in the master control chip, wherein the preprocessor is configured to run in a microcontroller independent of the master control chip, and wherein the microcontroller is connected to a power supply and the PSE chip.

6. The PSE of claim 1, further comprising a volatile memory disposed in the master control processor, wherein the master control processor is configured to detect whether data in the volatile memory disappears to obtain a detection result, and wherein the preprocessor is further configured to determine whether the master control processor starts upon power-on based on the detection result.

7. The PSE of claim 1, further comprising a volatile memory, coupled to the master control processor, wherein the master control processor is configured to detect whether data in the volatile memory disappears to obtain a detection result, and wherein the preprocessor is further configured to determine whether the master control processor starts upon power-on based on the detection result.

8. The PSE of claim 1, further comprising a volatile memory disposed in the master control processor, and wherein the preprocessor is configured to:

detect whether data in the volatile memory disappears to obtain a detection result; and

determine whether the master control processor starts upon power-on based on the detection result.

9. The PSE of claim 1, further comprising a volatile memory coupled to the master control processor, and wherein the preprocessor is configured to:

detect whether data in the volatile memory disappears to obtain a detection result; and

determine whether the master control processor starts upon power-on based on the detection result.

10. The PSE of claim 1, wherein the master control processor is configured to calculate, using a preset logical algorithm, a logical result according to a clock signal, a reset signal and a related state parameter of the master control processor, and wherein the preprocessor is further configured to:

obtain the logical result from the master control processor; and

determine according to the logical result, whether the master control processor starts upon power-on.

11. The PSE of claim 1, wherein the preprocessor is further configured to:

calculate, using a preset logical algorithm, a logical result according to a clock signal, a reset signal and a related state parameter of the master control processor; and

determine according to the logical result, whether the master control processor starts upon power-on.

12. A method for power over Ethernet (PoE) implemented by an Ethernet power sourcing equipment (PSE), wherein the method comprises:

determining, by a preprocessor, whether a master control processor starts upon power-on, wherein the Ethernet PSE comprises the preprocessor, the master control processor, a PSE chip and a power supplying port;

controlling, by the preprocessor when the master control processor starts upon power-on, the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD);

controlling, by the preprocessor according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD;

running, by the master control processor, BOOT of a basic input/output system (BIOS) during the master control processor starting upon power-on;

executing a main program during the master control processor starting upon power-on;

determining, by the master control processor, whether the PSE chip has supplied power to a PD after completing the master control processor starting upon power-on;

obtaining, by the master control processor, state information of the PSE chip when the PSE chip has supplied power to the PD;

using, by the master control processor, the state information as a start state for subsequently controlling the PSE chip; and

initializing, by the master control processor, the PSE chip when the PSE chip has not supplied power to the PD.

13. The method for PoE of claim 12, wherein controlling the PSE chip to power on the valid PD comprises:

obtaining, by the preprocessor, total output power for a plurality of PDs;

obtaining, by the preprocessor, agreed power of each of the PDs;

determining, by the preprocessor, a to-be-powered-on PD from each of the PDs according to the total output power and the agreed power of each of the PDs; and

controlling, by the preprocessor, the PSE chip to power on the to-be-powered-on PD.

14. The method for PoE of claim 12, wherein determining whether the master control processor starts upon power-on comprises:

detecting, by the preprocessor, whether data in a volatile memory disappears, wherein the volatile memory is disposed in the master control processor; and

determining, by the preprocessor, whether the master control processor starts upon power-on based on the detecting.

15. The method for PoE of claim 12, wherein determining whether the master control processor starts upon power-on comprises:

detecting, by the preprocessor, whether data in a volatile memory disappears, wherein the volatile memory is coupled to the master control processor; and

determining, by the preprocessor, whether the master control processor starts upon power-on based on the detecting.

16. The method for PoE of claim 12, wherein determining whether the master control processor starts upon power-on comprises:

calculating, by the preprocessor using a preset logical algorithm, a logical result according to a clock signal, a reset signal and a related state parameter of the master control processor; and

determining, by the preprocessor, according to the logical result, whether the master control processor starts upon power-on.

17. The method for PoE of claim 12, wherein determining whether the master control processor starts upon power-on comprises:

calculating, by the master control processor using a preset logical algorithm, a logical result according to a clock signal, a reset signal and a related state parameter of the master control processor; and

determining, by the preprocessor, according to the logical result, whether the master control processor starts upon power-on.

18. The method for PoE of claim 12, wherein the PSE comprises a master control chip, wherein the method further comprises running the preprocessor before the master control processor loads the main program, and wherein the preprocessor and the master control processor run in the master control chip.

19. The method for PoE of claim 12, wherein the PSE comprises a master control chip, wherein the method further comprises running the preprocessor before the master control processor skips to the main program, and wherein the preprocessor and the master control processor run in the master control chip.

20. The method for PoE of claim 12, wherein the PSE comprises a master control chip, wherein the method further comprises running the preprocessor in a microcontroller independent of the master control chip, wherein the master control processor runs in the master control chip.