Systems, apparatuses, and methods for performing delta decoding on packed data elements

• US 10,671,392 B2
• Filed: 07/31/2018
• Issued: 06/02/2020
• Est. Priority Date: 12/28/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ould-Ahmed-Vall, Elmoustapha, Willhalm, Thomas, Drysdale, Tracy Garrett
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US16/051,316
• Publication Number:
  US 20190065200A1
• Time in Patent Office: 672 Days
• Field of Search: None
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence

Abstract

Systems, apparatuses, and methods for performing delta decoding on packed data elements of a source and storing the results in packed data elements of a destination using a single packed delta decode instruction are described. A processor may include a decoder to decode an instruction, and execution unit to execute the decoded instruction to calculate for each packed data element position of a source operand, other than a first packed data element position, a value that comprises a packed data element of that packed data element position and all packed data elements of packed data element positions that are of lesser significance, store a first packed data element from the first packed data element position of the source operand into a corresponding first packed data element position of a destination operand, and for each calculated value, store the value into a corresponding packed data element position of the destination operand.

Claims

1. A method comprising:

decoding a single instruction into a decoded single instruction with a decoder of a processor; and

executing, by an execution unit of the processor, the decoded single instruction that identifies a source operand having a plurality of packed data elements and a destination operand to;

input a first packed data element from a first packed data element position of the source operand and a second packed data element from a second packed data element position of the source operand to a first adder, and generate a first value that is a sum of the first packed data element and the second packed data element,

input the first value from the first adder and a third packed data element from a third packed data element position of the source operand to a second adder, and produce a second value that is a sum of the first value and the third packed data element,

input a fourth packed data element from a fourth packed data element position of the source operand to a third adder, and produce a third value that is a sum of the fourth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a fifth packed data element from a fifth packed data element position of the source operand to a fourth adder, and produce a fourth value that is a sum of the fifth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a sixth packed data element from a sixth packed data element position of the source operand to a fifth adder, and produce a fifth value that is a sum of the sixth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a seventh packed data element from a seventh packed data element position of the source operand to a sixth adder, and produce a sixth value that is a sum of the seventh packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input an eighth packed data element from an eighth packed data element position of the source operand to a seventh adder, and produce a seventh value that is a sum of the eighth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance, and

store the first packed data element from the first packed data element position of the source operand into a first packed data element position of the destination operand, the first value into a second packed data element position of the destination operand, the second value into a third packed data element position of the destination operand, the third value into a fourth packed data element position of the destination operand, the fourth value into a fifth packed data element position of the destination operand, the fifth value into a sixth packed data element position of the destination operand, the sixth value into a seventh packed data element position of the destination operand, and the seventh value into an eighth packed data element position of the destination operand.

2. The method of claim 1, wherein the source operand and destination operand are vector registers.

3. The method of claim 2, wherein the vector registers are 256-bits in size.

4. The method of claim 2, wherein the vector registers are 512-bits in size.

5. The method of claim 2, wherein the vector registers are 1024-bits in size.

6. The method of claim 1, wherein each of the packed data elements of the source operand are 64-bits in size.

7. The method of claim 1, wherein each of the packed data elements of the source operand and the destination operand are a same size.

8. A processor comprising:

a decoder to decode a single instruction that includes a source operand having a plurality of packed data elements and a destination operand into a decoded single instruction; and

an execution unit to execute the decoded single instruction to;

input a first packed data element from a first packed data element position of the source operand and a second packed data element from a second packed data element position of the source operand to a first adder, and generate a first value that is a sum of the first packed data element and the second packed data element,

input the first value from the first adder and a third packed data element from a third packed data element position of the source operand to a second adder, and produce a second value that is a sum of the first value and the third packed data element,

input a fourth packed data element from a fourth packed data element position of the source operand to a third adder, and produce a third value that is a sum of the fourth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a fifth packed data element from a fifth packed data element position of the source operand to a fourth adder, and produce a fourth value that is a sum of the fifth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a sixth packed data element from a sixth packed data element position of the source operand to a fifth adder, and produce a fifth value that is a sum of the sixth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a seventh packed data element from a seventh packed data element position of the source operand to a sixth adder, and produce a sixth value that is a sum of the seventh packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input an eighth packed data element from an eighth packed data element position of the source operand to a seventh adder, and produce a seventh value that is a sum of the eighth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance, and

store the first packed data element from the first packed data element position of the source operand into a first packed data element position of the destination operand, the first value into a second packed data element position of the destination operand, the second value into a third packed data element position of the destination operand, the third value into a fourth packed data element position of the destination operand, the fourth value into a fifth packed data element position of the destination operand, the fifth value into a sixth packed data element position of the destination operand, the sixth value into a seventh packed data element position of the destination operand, and the seventh value into an eighth packed data element position of the destination operand.

9. The processor of claim 8, wherein the source operand and destination operand are vector registers of the processor.

10. The processor of claim 9, wherein the vector registers are 256-bits in size.

11. The processor of claim 9, wherein the vector registers are 512-bits in size.

12. The processor of claim 9, wherein the vector registers are 1024-bits in size.

13. The processor of claim 8, wherein each of the packed data elements of the source operand are 64-bits in size.

14. The processor of claim 8, wherein each of the packed data elements of the source operand and the destination operand are a same size.

15. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:

decoding a single instruction into a decoded single instruction with a decoder of a processor; and

executing, by an execution unit of the processor, the decoded single instruction that identifies a source operand having a plurality of packed data elements and a destination operand to;

input a first packed data element from a first packed data element position of the source operand and a second packed data element from a second packed data element position of the source operand to a first adder, and generate a first value that is a sum of the first packed data element and the second packed data element,

input the first value from the first adder and a third packed data element from a third packed data element position of the source operand to a second adder, and produce a second value that is a sum of the first value and the third packed data element,

input a fourth packed data element from a fourth packed data element position of the source operand to a third adder, and produce a third value that is a sum of the fourth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a fifth packed data element from a fifth packed data element position of the source operand to a fourth adder, and produce a fourth value that is a sum of the fifth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a sixth packed data element from a sixth packed data element position of the source operand to a fifth adder, and produce a fifth value that is a sum of the sixth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input a seventh packed data element from a seventh packed data element position of the source operand to a sixth adder, and produce a sixth value that is a sum of the seventh packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance,

input an eighth packed data element from an eighth packed data element position of the source operand to a seventh adder, and produce a seventh value that is a sum of the eighth packed data element and all packed data elements of packed data element positions of the source operand that are of lesser significance, and

store the first packed data element from the first packed data element position of the source operand into a first packed data element position of the destination operand, the first value into a second packed data element position of the destination operand, the second value into a third packed data element position of the destination operand, the third value into a fourth packed data element position of the destination operand, the fourth value into a fifth packed data element position of the destination operand, the fifth value into a sixth packed data element position of the destination operand, the sixth value into a seventh packed data element position of the destination operand, and the seventh value into an eighth packed data element position of the destination operand.

16. The non-transitory machine readable medium of claim 15, wherein the source operand and destination operand are vector registers.

17. The non-transitory machine readable medium of claim 16, wherein the vector registers are 256-bits in size.

18. The non-transitory machine readable medium of claim 16, wherein the vector registers are 512-bits in size.

19. The non-transitory machine readable medium of claim 16, wherein the vector registers are 1024-bits in size.

20. The non-transitory machine readable medium of claim 15, wherein each of the packed data elements of the source operand are 64-bits in size.

21. The non-transitory machine readable medium of claim 15, wherein each of the packed data elements of the source operand and the destination operand are a same size.