Method of semiconductor integrated circuit fabrication

• US 10,672,656 B2
• Filed: 10/05/2015
• Issued: 06/02/2020
• Est. Priority Date: 10/30/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shieh, Ming-Feng, Hsieh, Hung-Chang, Tseng, Wen-Hung
• Primary Examiner(s): Nguyen, Sophia T
• Application Number:
  US14/875,535
• Publication Number:
  US 20160027692A1
• Time in Patent Office: 1,702 Days
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28141 insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/4763 Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28, H01L21/44
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76861 Post-treatment or after-treatment not introducing additional chemical elements into the layer
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 : manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 : interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823821 : with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 : with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 : with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 : interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 : isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/485 : consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53233 : Copper alloys
• CPC Class Codes: H01L 23/53257 : the principal metal being a refractory metal
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 27/0924 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41775 : characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/435 : Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/4958 : with a multiple layer structure
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Claims

1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

providing a first conductive feature on a substrate and a second conductive feature in the substrate, wherein the first conductive feature is surrounded by a spacer and by a first dielectric layer;

forming a first hard mask (HM) as a top layer on the first conductive feature, wherein the forming the first HM includes forming a first trench by removing a portion of the first conductive feature and thereafter filling the first trench with a dielectric material;

depositing a second dielectric layer directly on the first dielectric layer and on the first HM;

selectively etching a first opening through the first and second dielectric layers, wherein the first opening exposes the second conductive feature, and wherein the selectively etching is performed such that the first and second dielectric layers have an etching selectivity with the first HM;

forming a first metal plug in the first opening to connect the second conductive feature;

removing the second dielectric layer;

forming a second HM as a top layer on the first metal plug;

forming a third dielectric layer over the first dielectric layer, over the first HM, and over the second HM;

simultaneously etching a plurality of second openings through the third dielectric layer such that the second openings are isolated from each other, wherein at least a first one of the second openings extends vertically through the first HM and exposes the first conductive feature, and wherein at least a second one of the second openings extends vertically through the second HM and exposes the first metal plug; and

forming second metal plugs in the second openings to connect to the first conductive feature and the first metal plug.

2. The method of claim 1, wherein the forming of the second HM includes:

recessing the first metal plug to form a second trench;

depositing a second HM material over the substrate, including a first portion filling in the second trench and a second portion extending beyond the second trench; and

removing the second portion of the second HM material.

3. The method of claim 1, wherein the first conductive feature includes a gate stack.

4. The method of claim 3, wherein the second conductive feature includes a source/drain region.

5. The method of claim 1, wherein portions of the second HM still remain on the first metal plug after the forming of the second metal plugs.

6. The method of claim 1, wherein at least a first one of the second metal plugs is formed to have a different lateral dimension from at least a second one of the second metal plugs.

7. The method of claim 1, wherein the first opening is etched such that the first opening is spaced apart from the spacer by a portion of the first dielectric layer.

8. The method of claim 1, wherein the forming the first trench comprises performing an etching process to an entire upper surface of the first conductive feature.

9. A method comprising:

receiving a substrate having a first dielectric layer disposed thereupon, a first conductive feature and spacers disposed within the first dielectric layer, and a plurality of second conductive features disposed within the substrate;

recessing an entire upper portion of the first conductive feature to form a first trench, wherein side surfaces of the first trench are defined by the spacers, and wherein a bottom surface of the first trench is defined by a remaining portion of the first conductive feature after the recessing;

filling the first trench to form a first hard mask, wherein the first dielectric layer, the first hard mask, and the spacers are formed to have substantially co-planar upper surfaces;

forming a second dielectric layer directly on the first dielectric layer and the first hard mask;

recessing a portion of the first dielectric layer and a portion of the second dielectric layer to define a plurality of second trenches that each extends through the first and second dielectric layers and that each exposes a respective one of the second conductive features, wherein the recessing is performed using an etching process in which the first and second dielectric layers have an etching selectivity with the first hard mask;

forming a plurality of first plugs in the second trenches, wherein each of the first plugs is electrically coupled to a respective one of the second conductive features;

removing the second dielectric layer;

recessing a portion of each of the first plugs to define a plurality of third trenches that exposes an upper surface of the first plugs;

forming a plurality of second hard masks within the third trenches;

forming a third dielectric layer over the first dielectric layer, the spacers, the first hard mask, and the second hard masks;

forming a plurality of second plugs that each extends vertically through the third dielectric layer and through the second hard masks to electrically couple to the first plug, wherein a first one of the second plugs is formed to be adjacent to the first conductive feature, and wherein a second one of the second plugs is formed to be away from the first conductive feature such that at least one of the first plugs is located between the first conductive feature and the second one of the second plugs; and

forming a third plug that extends vertically through the third dielectric layer and through the first hard mask to electrically couple to the first conductive feature.

10. The method of claim 9, wherein the first conductive feature includes a gate feature.

11. The method of claim 10, wherein the second conductive features each includes a source/drain feature.

12. The method of claim 9, wherein the recessing of the first dielectric layer to define the second trenches uses an etchant selected to avoid etching of the first hard mask to expose the first conductive feature.

13. The method of claim 9, wherein the forming of the second plugs includes:

recessing a first portion of the third dielectric layer and the second hard masks to define a plurality of fourth trenches that extends vertically through the third dielectric layer and the second hard masks, wherein the fourth trenches expose the first plugs; and

depositing the second plugs within the fourth trenches.

14. The method of claim 13, wherein the forming of the third plug includes:

recessing a second portion of the third dielectric layer and the first hard mask to define a fifth trench that extends vertically through the third dielectric layer and the first hard mask, wherein the fifth trench exposes the first conductive feature, and wherein the recessing of the first portion of the third dielectric layer and the recessing of the second portion of the third dielectric layer are simultaneously performed; and

depositing the third plug within the fifth trench.

15. The method of claim 9, wherein the first plug, the second plugs, and the third plug are all visible in a same cross-sectional side view.

16. A method comprising:

receiving a substrate having disposed thereupon;

a first conductive feature and a second conductive feature, wherein a top surface of the first conductive feature is above a top surface of the second conductive feature;

a first dielectric layer disposed alongside the first conductive feature and on the second conductive feature; and

a spacer disposed between the first conductive feature and the first dielectric layer;

partially removing the first conductive feature and forming a first hard mask on a remaining portion of the first conductive feature, wherein a top surface of the first hard mask is substantially coplanar with a top surface of the first dielectric layer and with a top surface of the spacer, and wherein the first hard mask and the first dielectric layer have different material compositions;

forming a second dielectric layer directly on the first dielectric layer and the first hard mask;

etching the first dielectric layer to form a first trench in the first dielectric layer and the second dielectric layer, wherein the first trench exposes the second conductive feature, wherein the etching is configured to have an etching selectivity between the first and second dielectric layers and the first hard mask, such that the etching etches away the first and second dielectric layers without removing the first hard mask;

forming a first plug in the first trench and on the second conductive feature;

removing the second dielectric layer;

forming a second hard mask on the first plug;

forming a third dielectric layer over;

the first dielectric layer, the spacer, the first hard mask, and the second hard mask;

simultaneously etching a first opening and a second opening, wherein the first opening is etched to extend vertically through the third dielectric layer and the second hard mask to expose the first plug, and wherein the second opening is etched to extend vertically through the third dielectric layer and the first hard mask to expose the first conductive feature; and

filling the first opening and the second opening with a conductive material, thereby forming a second plug in the first opening and a third plug in the second opening.

17. The method of claim 16, wherein the first conductive feature includes a gate stack.

18. The method of claim 17, wherein the second conductive feature includes a source/drain feature.

19. The method of claim 16, wherein the forming of the first trench uses an etchant composition selected to avoid substantial etching of the first hard mask.

20. The method of claim 16, wherein a top surface of the second hard mask is substantially coplanar with the top surface of the first hard mask.