Semiconductor device

• US 10,672,781 B2
• Filed: 12/23/2019
• Issued: 06/02/2020
• Est. Priority Date: 06/21/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Byoung Il, Gu, Ji Mo, Lee, Tak, Cha, Jun Ho
• Primary Examiner(s): Green, Telly D
• Application Number:
  US16/724,444
• Publication Number:
  US 20200144277A1
• Time in Patent Office: 162 Days
• Field of Search: None
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction.

Claims

1. A semiconductor device comprising:

a peripheral circuit region provided on a base substrate and including circuit devices; and

a memory cell region provided on a substrate disposed on the base substrate, the substrate having a first region and a second region,

wherein the memory cell region includes;

a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region;

first and second isolation regions extending in the second direction, while penetrating through the gate electrode stack, in the first and second regions;

string isolation regions disposed between the first isolation region and the second isolation region only in the first region, and extending in the second direction while penetrating through at least one uppermost gate electrode of the gate electrode stack; and

a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in the first and second regions, and spaced apart from each other in the second direction while penetrating a portion of the gate electrode stack.

2. The semiconductor device of claim 1,

wherein the string isolation regions are alternately arranged with the plurality of auxiliary isolation regions in the first region.

3. The semiconductor device of claim 1,

wherein the plurality of auxiliary isolation regions are disposed to have two or more spacing distances different from each other.

4. The semiconductor device of claim 1,

wherein a width of each of the plurality of auxiliary isolation regions in a third direction perpendicular to the first and second directions is equal to or narrower than a width of each of the first and second isolation regions in the third direction.

5. The semiconductor device of claim 1,

wherein a width of each of the plurality of auxiliary isolation regions in a third direction perpendicular to the first and second directions is greater than a width of each of the string isolation regions in the third direction.

6. The semiconductor device of claim 1,

wherein each of the first and second isolation regions and each of the plurality of auxiliary isolation regions comprise an insulating layer and a conductive layer filling the insulating layer, and

the conductive layer is in contact with the substrate to be connected the substrate in the first and second isolation regions, and is disposed to be spaced apart from the substrate by the insulating layer in the plurality of auxiliary isolation regions.

7. A semiconductor device comprising:

a peripheral circuit region provided on a base substrate and including circuit devices; and

a memory cell region provided on a substrate disposed on the base substrate, the substrate having a first region and a second region,

wherein the memory cell region includes;

a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region;

first and second isolation regions extending in the second direction, while penetrating through the gate electrode stack, in the first and second regions;

string isolation regions disposed between the first isolation region and the second isolation region only in the first region, and extending in the second direction while penetrating through at least one uppermost gate electrode of the gate electrode stack; and

a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in the second region, and spaced apart from each other in the second direction while penetrating a portion of the gate electrode stack.

8. The semiconductor device of claim 7,

wherein the plurality of auxiliary isolation regions are spaced apart from the string isolation regions.

9. The semiconductor device of claim 7,

wherein the plurality of auxiliary isolation regions are disposed to have two or more spacing distances different from each other.

10. The semiconductor device of claim 7,

wherein each of the first and second isolation regions and each of the plurality of auxiliary isolation regions comprise an insulating layer and a conductive layer filling the insulating layer, and

the conductive layer is in contact with the substrate to be connected the substrate in the first and second isolation regions, and is disposed to be spaced apart from the substrate by the insulating layer in the plurality of auxiliary isolation regions.

11. A semiconductor device comprising:

a peripheral circuit region provided on a base substrate and including circuit devices; and

a memory cell region provided on a substrate disposed on the base substrate, the substrate having a first region and a second region,

wherein the memory cell region includes;

a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region;

first and second isolation regions extending in the second direction, while penetrating through the gate electrode stack, in the first and second regions;

string isolation regions disposed between the first isolation region and the second isolation region in the first region, and extending in the second direction while penetrating through at least one uppermost gate electrode of the gate electrode stack; and

a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction while penetrating a portion of the gate electrode stack,

wherein each of the first and second isolation regions and each of the plurality of auxiliary isolation regions comprise an insulating layer and a conductive layer filling the insulating layer.

12. The semiconductor device of claim 11,

wherein the conductive layer is in contact with the substrate to be connected the substrate in the first and second isolation regions, and is disposed to be spaced apart from the substrate by the insulating layer in the plurality of auxiliary isolation regions.

13. The semiconductor device of claim 11,

wherein the plurality of auxiliary isolation regions are disposed to have two or more spacing distances different from each other.

14. The semiconductor device of claim 11,

wherein a width of each of the plurality of auxiliary isolation regions in a third direction perpendicular to the first and second directions is equal to or narrower than a width of each of the first and second isolation regions in the third direction.

15. The semiconductor device of claim 11,

wherein a width of each of the plurality of auxiliary isolation regions in a third direction perpendicular to the first and second directions is greater than a width of each of the string isolation regions in the third direction.

16. The semiconductor device of claim 11,

wherein the string isolation regions are alternately arranged with the plurality of auxiliary isolation regions in the first region.

17. The semiconductor device of claim 11,

wherein lateral surfaces of each of the plurality of auxiliary isolation regions in the first region are in contact with lateral surfaces of the string isolation regions.

18. The semiconductor device of claim 11,

wherein the plurality of auxiliary isolation regions in the second region are spaced apart from the string isolation regions.

19. The semiconductor device of claim 11,

wherein the at least one of the plurality of gate electrodes is partially divided into a first portion and a second portion divided by a corresponding auxiliary isolation region in the second region, and

wherein the first portion and the second portion is connected between the corresponding auxiliary isolation region and another auxiliary isolation region adjacent thereto.

20. The semiconductor device of claim 11,

wherein the plurality of auxiliary isolation regions are disposed to have two or more spacing distances different from each other.