Active CMOS recovery units for wireless power transmission

• US 10,673,351 B2
• Filed: 06/08/2018
• Issued: 06/02/2020
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Hajimiri, Seyed Ali, Abiri, Behrooz, Bohn, Florian
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US16/004,198
• Publication Number:
  US 20190173389A1
• Time in Patent Office: 725 Days
• Field of Search: 307149
• CPC Class Codes: H02J 5/00 Circuit arrangements for transfer of electric power between ac networks and dc networks H02J3/36 takes precedence
• CPC Class Codes: H02J 50/005 Mechanical details of housing or structure aiming to accommodate the power transfer means, e.g. mechanical integration of coils, antennas or transducers into emitting or receiving devices
• CPC Class Codes: H02J 50/10 using inductive coupling
• CPC Class Codes: H02J 50/27 characterised by the type of receiving antennas, e.g. rectennas
• CPC Class Codes: H02M 1/123 Suppression of common mode voltage or current
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/23 arranged for operation in parallel H02M7/2176 takes precedence

Abstract

A rectifying circuit includes, in part, first and second NMOS transistors, an impedance matching network, and an RF block circuit. The source and gate terminals of the first NMOS transistor respectively receive the ground potential and a biasing voltage. The second NMOS transistor has a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential. The impedance matching network is disposed between the antenna and the drain terminals of the first and second NMOS transistors. The RF block circuit is coupled between the drain terminals of the first and second NMOS transistors and the output terminal of the rectifying circuit. The RF block circuit is adapted to prevent the RF signal from flowing into the output terminal of the rectifying circuit.

Claims

1. A rectifying circuit adapted to rectify an RF signal supplied by an antenna, the rectifying circuit comprising:

a first MOS transistor having a source terminal receiving a ground voltage and a gate terminal receiving a biasing voltage;

a second MOS transistor having a source terminal receiving the ground voltage and a gate terminal receiving the biasing voltage, wherein a gate terminal of the first MOS transistor is coupled to a drain terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is coupled to a drain terminal of the first MOS transistor;

a first inductive element coupled between an output terminal of the rectifying circuit and the drain terminal of the first MOS transistor;

a second inductive element coupled between the output terminal and the drain terminal of the second MOS transistor; and

a first capacitive element coupled between the output terminal and a ground terminal supplying the ground voltage.

2. The rectifying circuit of claim 1 further comprising:

a second capacitive element disposed between the gate terminal of the first MOS transistor and the drain terminal of the second MOS transistor; and

a third capacitive element disposed between the gate terminal of the second MOS transistor and the drain terminal of the first MOS transistor.

3. The rectifying circuit of claim 1 further comprising:

a biasing circuit supplying the biasing voltage to the gate terminals of the first and second MOS transistors.

4. The rectifying circuit of claim 1 wherein said biasing circuit supplies a fixed voltage.

5. The rectifying circuit of claim 1 wherein said biasing circuit supplies the biasing voltage in response to an output voltage sensed at the output terminal.

6. The rectifying circuit of claim 1 wherein said rectifying circuit further comprises:

a first resistive element disposed between the biasing circuit and the gate terminal of the first MOS transistor; and

a second resistive element disposed between the biasing circuit and the gate terminal of the second MOS transistor.

7. The rectifying circuit of claim 1 wherein said RF signal is applied between the drain terminals of the first and second MOS transistors.

8. The rectifying circuit of claim 1 wherein said RF signal is applied between the drain terminal of one of the first or second MOS transistors and the ground terminal.

9. The rectifying circuit of claim 1 wherein said rectifying circuit further comprises:

a third inductive element disposed between the biasing circuit and the gate terminal of the first MOS transistor; and

a fourth inductive element disposed between the biasing circuit and the gate terminal of the second MOS transistor.

10. A method of rectifying an RF signal delivered by an antenna, the method comprising:

applying a biasing voltage to a gate terminal of a first MOS transistor having a source terminal receiving a ground potential;

applying the biasing voltage to a gate terminal of a second MOS transistor, wherein the gate terminal of the first MOS transistor is coupled to a drain terminal of the second MOS transistor, and the gate terminal of the second MOS transistor is coupled to a drain terminal of the first MOS transistor, and wherein a source terminal of the second MOS transistor receives the ground potential;

coupling a first inductive element between an output terminal supplying the rectified signal and the drain terminal of the first MOS transistor;

coupling a second inductive element between the output terminal and the drain terminal of the second MOS transistor; and

coupling a capacitive element between the output terminal and the ground terminal.

11. The method of claim 10 further comprising:

supplying the biasing voltage to the gate terminal of the first MOS transistor via a second capacitive element; and

supplying the biasing voltage to the gate terminal of the second MOS transistor via a third capacitive element.

12. The method of claim 10 further comprising:

supplying the biasing voltage via a fixed voltage supply.

13. The method of claim 10 further comprising:

supplying the biasing voltage in response to a voltage sensed at the output terminal.

14. The method of claim 10 further comprising:

applying the RF signal between the drain terminals of the first and second MOS transistors.

15. The method of claim 10 further comprising:

applying the RF signal between the drain terminal of one of the first or second MOS transistors and the ground terminal.

16. The method of claim 10 further comprising:

coupling a third inductive element between the gate terminal of the first MOS transistor and the biasing circuit; and

coupling a fourth inductive element between the gate terminal of the second MOS transistor and the biasing circuit.