Array substrate, display panel, display device and driving method

  • US 10,679,565 B2
  • Filed: 11/07/2017
  • Issued: 06/09/2020
  • Est. Priority Date: 04/27/2017
  • Status: Active Grant
First Claim
Patent Images

1. An array substrate, comprising:

  • a plurality of first pixel units arranged in an array in a first region;

    a first gate driving circuit;

    a second gate driving circuit;

    a plurality of first gate lines connected with the first gate driving circuit;

    a plurality of second gate lines connected with the second gate driving circuit,a plurality of second pixel units arranged in an array in a second region;

    a plurality of third pixel units arranged in an array in a third region;

    a plurality of third gate lines connected with the first gate driving circuit; and

    a plurality of fourth gate lines connected with the second gate driving circuit, wherein;

    a first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion of the plurality of first pixel units is connected with one of the plurality of first state lines;

    a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion of the plurality of first pixel units is connected with one of the plurality of second gate lines;

    a first portion of the plurality of second pixel units is connected with the plurality of first gate lines, and each second pixel unit in the first portion of the plurality of second pixel units is connected with one of the plurality of first gate lines;

    a second portion of the plurality of second pixel units is connected with the plurality of third gate lines, and each second pixel unit in the second portion of the plurality of second pixel units is connected with one of the plurality of third gate lines;

    a first portion of the plurality of third pixel units is connected with the plurality of second gate lines, and each third pixel unit in the first portion of the plurality of third pixel units is connected with one of the plurality of second gate lines;

    a second portion of the plurality of third pixel units is connected with the plurality of fourth gate lines, and each third pixel unit in the second portion of the plurality of third pixel units is connected with one of the plurality of fourth gate lines;

    whereinfirst pixel units in a (2n−

    1)th row and second pixel units in the (2n−

    1)th row are connected with an nth first gate line;

    first pixel units in a 2nth row and third pixel units in the 2nth row are connected with an nth second gate line;

    second pixel units in the 2nth row are connected with an nth third gate line;

    third pixel units in the (2n−

    1)th row are connected with an nth fourth gate line; and

    n is an integer greater than 0, n≤

    N/2, and N is a total number of rows of pixel units in respective regions.

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