Display device, display module, and electronic device
First Claim
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1. A display device comprising:
- a gate driver; and
a pixel portion,wherein the pixel portion comprises a plurality of pixels,wherein the gate driver is configured to output a first scan signal to a first gate line in a first frame period,wherein the gate driver is configured to output a second scan signal to a second gate line in a second frame period,wherein the gate driver is configured to output a third scan signal to a third gate line in the first frame period,wherein the second gate line is a gate line next to the first gate line,wherein the third gate line is a gate line next to the second gate line,wherein the plurality of pixels are configured to hold data signals, which are written in the plurality of pixels in the first frame period, in the first frame period and the second frame period,wherein the plurality of pixels each comprise a transistor,wherein the transistor comprises an oxide semiconductor in a channel formation region, andwherein the oxide semiconductor comprises indium and zinc.
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Abstract
A display device or the like with a novel structure which can ensure a sufficiently long period for writing data signals in pixels is provided. A display device or the like with a novel structure which can display an image of one frame without greatly degrading display quality is provided. The display device includes a gate driver and a pixel portion. The pixel portion includes a plurality of pixels. The gate driver is configured to output a first scan signal to a first gate line in a first frame period. The gate driver is configured to output a second scan signal to a second gate line in a second frame period. The second gate line is a gate line next to the first gate line. The pixels are configured to hold data signals, which are written in the pixels in the first frame period, in the first frame period and the second frame period.
16 Citations
18 Claims
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1. A display device comprising:
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a gate driver; and a pixel portion, wherein the pixel portion comprises a plurality of pixels, wherein the gate driver is configured to output a first scan signal to a first gate line in a first frame period, wherein the gate driver is configured to output a second scan signal to a second gate line in a second frame period, wherein the gate driver is configured to output a third scan signal to a third gate line in the first frame period, wherein the second gate line is a gate line next to the first gate line, wherein the third gate line is a gate line next to the second gate line, wherein the plurality of pixels are configured to hold data signals, which are written in the plurality of pixels in the first frame period, in the first frame period and the second frame period, wherein the plurality of pixels each comprise a transistor, wherein the transistor comprises an oxide semiconductor in a channel formation region, and wherein the oxide semiconductor comprises indium and zinc. - View Dependent Claims (2, 3, 4, 5, 17)
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6. A display device comprising:
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a gate driver; and a pixel portion comprising; a plurality of pixels; a first display region; and a second display region, wherein the first display region is a region where a first scan signal is output to a first gate line and a second scan signal is output to a second gate line, and wherein the second display region is a region where a third scan signal is output to a third gate line and a fourth scan signal is output to a fourth gate line, wherein the gate driver is configured to output the first scan signal, the third scan signal, and the fourth scan signal in a first frame period, wherein the gate driver is configured to output the second scan signal, the third scan signal, and the fourth scan signal in a second frame period, wherein the second gate line is a gate line next to the first gate line, wherein the third gate line is a gate line next to the second gate line, wherein the fourth gate line is a gate line next to the third gate line, and wherein the pixels included in the first display region are configured to hold data signals, which are written in the pixels in the first frame period, in the first frame period and the second frame period. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A display device comprising:
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a gate driver; a source driver; a pixel portion comprising a first pixel, a second pixel, and a third pixel; a data line electrically connected to the first pixel, the second pixel, and the third pixel; a first gate line electrically connected to the first pixel; a second gate line electrically connected to the second pixel; and a third gate line electrically connected to the third pixel, wherein the gate driver is configured to output a first scan signal to the first gate line in a first frame period, wherein the gate driver is configured to output a second scan signal to the second gate line in a second frame period, wherein the gate driver is configured to output a third scan signal to the third gate line in the first frame period, wherein the second gate line is a gate line next to the first gate line, wherein the third gate line is a gate line next to the second gate line, wherein the source driver is configured to output a data signal to the data line in the first frame period, wherein the first pixel is configured to hold the data signal in the first frame period and the second frame period, wherein the first pixel the second pixel, and the third pixel each comprise a transistor, wherein the transistor comprises an oxide semiconductor in a channel formation region, and wherein the oxide semiconductor comprises indium and zinc. - View Dependent Claims (13, 14, 15, 16, 18)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsMori, Hidenori, Matsumoto, Hironori, Fukutome, Takahiro
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Primary Examiner(s)Sadio, Insa
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Application NumberUS15/450,292Publication NumberTime in Patent Office1,198 DaysField of SearchUS Class CurrentCPC Class CodesG06F 3/0412 Digitisers structurally int...G09G 2300/0426 Layout of electrodes and co...G09G 2300/0809 Several active elements per...G09G 2300/0842 forming a memory circuit, e...G09G 2310/0213 controlling the sequence of...G09G 2320/103 Detection of image changes,...G09G 2340/0435 Change or adaptation of the...G09G 3/3233 with pixel circuitry contro...G09G 3/3648 using an active matrix G09G...G09G 3/3677 suitable for active matrice...
