Method for polar coding and apparatus

• US 10,693,590 B2
• Filed: 07/09/2019
• Issued: 06/23/2020
• Est. Priority Date: 09/18/2017
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Luo, Hejia, Du, Yinggang, Li, Rong, Huang, Lingchen, Chen, Ying
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US16/506,765
• Publication Number:
  US 20190334654A1
• Time in Patent Office: 350 Days
• Field of Search: 714776, 714775, 714774
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data

Abstract

Embodiments of this application provide a method for coding in a wireless communication network. A communication device interleave a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI); wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence. The devices add d first CRC bits on the first interleaved sequence to obtain a second bit sequence, interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence, and polar encode the second interleaved sequence to obtain the encoded sequence.

Claims

1. A method for coding, performed by a device in a wireless communication network, comprising:

inputting a first bit sequence, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI);

interleaving the first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence;

adding a number of Cyclic Redundancy Check (CRC) bits on the first interleaved sequence to obtain a second bit sequence;

interleaving on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence;

polar encoding the second interleaved sequence to obtain the encoded sequence; and

outputting the encoded sequence.

2. The method according to claim 1, wherein the bits for indicating timing further comprises one bit for indicating half frame indication (HFI), wherein the one bit for indicating the HFI is placed in a position indicated by the smallest sequence number in the first interleaved sequence.

3. The method according to claim 2, wherein the smallest sequence number in the first interleaved sequence is 0.

4. The method according to claim 1, wherein the number of CRC bits is 24.

5. The method according to claim 1, wherein the interleave pattern is:

(0 2 3 5 7 10 11 12 14 15 18 19 21 26 30 31 32 1 4 6 8 13 16 20 25 27 33 9 17 23 28 34 29 35 36 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54

     55).

6. The method according to claim 1, wherein bits for indicating timing further comprises a set of bits for indicating system frame number (SFN), part of the set of bits for indicating the SFN are placed in positions indicated by sequence numbers of 6, 10, 30, 8, 17, 18, and 23 in the first interleaved sequence.

7. The method according to claim 1, wherein polar encoding the second interleaved sequence to obtain the encoded sequence comprises:

encoding the second interleaved sequence according to an encoding formula, to obtain an encoded bit sequence, wherein a length of the encoded bit sequence is N; and

wherein the encoding formula is;

x₁^N=u₁^NG_N

wherein u₁^N=(u₁, u₂, . . . , u_N) is a binary row vector representing the second interleaved sequence, x₁^N=(x₁, x₂, . . . , x_N) is the encoded sequence, and G_N is a polar code generating matrix of N rows and N columns.

8. A device in a wireless communication network, comprising:

at least one processor and a memory storing program instructions for execution by the at least one processor;

wherein when executed by the at least one processor, the program instructions cause the device to;

input a first bit sequence, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI);

interleave the first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence;

add a number of Cyclic Redundancy Check (CRC) bits on the first interleaved sequence to obtain a second bit sequence;

interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence;

polar encode the second interleaved sequence to obtain the encoded sequence; and

output the encoded sequence.

9. The device according to claim 8, wherein the bits for indicating timing further comprises one bit for indicating half frame indication (HFI), the one bit for indicating the HFI is placed in a position indicated by the smallest sequence number in the first interleaved sequence.

10. The device according to claim 9, wherein the smallest sequence number in the first interleaved sequence is 0.

11. The device according to claim 8, wherein the number of CRC bits is 24.

12. The device according to claim 8, wherein the interleave pattern is:

(0 2 3 5 7 10 11 12 14 15 18 19 21 26 30 31 32 1 4 6 8 13 16 20 25 27 33 9 17 23 28 34 29 35 36 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54

     55).

13. The device according to claim 8, wherein bits for indicating timing further comprises a set of bits for indicating system frame number (SFN), part of the set of bits for indicating the SFN are placed in positions indicated by sequence numbers of 6, 10, 30, 8, 17, 18, and 23 in the first interleaved sequence.

14. The device according to claim 8, wherein the instructions cause the device to:

encode the second interleaved sequence according to an encoding formula, to obtain an encoded bit sequence, wherein a length of the encoded bit sequence is N; and

wherein the encoding formula is;

x₁^N=u₁^NG_N

wherein u₁^N=(u₁, u₂, . . . , u_N) is a binary row vector representing the second interleaved sequence, x₁^N=(x₁, x₂, . . . , x_N) is the encoded sequence, and G_N is a polar code generating matrix of N rows and N columns.

15. The device according to claim 8, wherein the device is a base station or a user terminal.

16. A device, comprising:

an input interface circuit, a logic circuit, and an output interface circuit;

wherein the input interface circuit, configured to input a first bit sequence, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI);

wherein the logic circuit, configured to interleave the first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence;

add a number of Cyclic Redundancy Check (CRC) bits on the first interleaved sequence to obtain a second bit sequence;

interleave on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence; and

polar encode the second interleaved sequence to obtain the encoded sequence; and

wherein the output interface circuit, configured to output the encoded sequence.

17. The device according to claim 16, wherein the bits for indicating timing further comprises one bit for indicating half frame indication (HFI), the one bit for indicating the HFI is placed in a position indicated by the smallest sequence number in the first interleaved sequence.

18. The device according to claim 17, wherein the smallest sequence number in the first interleaved sequence is 0.

19. The device according to claim 16, wherein the number of CRC bits is 24.

20. The device according to claim 16, wherein the interleave pattern is:

(0 2 3 5 7 10 11 12 14 15 18 19 21 26 30 31 32 1 4 6 8 13 16 20 25 27 33 9 17 23 28 34 29 35 36 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54

     55).

21. The device according to claim 16, wherein bits for indicating timing further comprises a set of bits for indicating system frame number (SFN), wherein part of the set of bits for indicating the SFN are placed in positions indicated by sequence numbers of 6, 10, 30, 8, 17, 18, and 23 in the first interleaved sequence.

22. The device according to claim 16, wherein the logic circuit, configured to:

encode the second interleaved sequence according to an encoding formula, to obtain an encoded bit sequence, wherein a length of the encoded bit sequence is N; and

wherein the encoding formula is;

x₁^N=u₁^NG_N

wherein u₁^N=(u₁, u₂, . . . , u_N) is a binary row vector representing the second interleaved sequence, x₁^N=(x₁, x₂, . . . , x_N) is the encoded sequence, and G_N is a polar code generating matrix of N rows and N columns.

23. A non-transitory computer readable medium storing program codes thereon for execution by one or more processors in a communication device, wherein the program codes comprise instructions for:

interleaving a first bit sequence to obtain a first interleaved sequence having sequence number starting with a sequence number of 0, wherein the first bit sequence comprises bits for indicating timing, wherein the bits for indicating timing comprises a set of bits for indicating synchronization signal block index (SSBI);

wherein the set of bits for indicating SSBI are placed in positions indicated by sequence numbers of 2, 3 and 5 in the first interleaved sequence;

adding Cyclic Redundancy Check (CRC) bits on the first interleaved sequence to obtain a second bit sequence;

interleaving on the second bit sequence according to an interleave pattern to obtain a second interleaved sequence; and

polar encoding the second interleaved sequence to obtain the encoded sequence.

24. The non-transitory computer readable medium according to claim 23, wherein the bits for indicating timing further comprises one bit for indicating half frame indication (HFI), the one bit for indicating the HFI is placed in a position indicated by the smallest sequence number in the first interleaved sequence.

25. The non-transitory computer readable medium according to claim 24, wherein the smallest sequence number in the first interleaved sequence is 0.

26. The non-transitory computer readable medium according to claim 23, wherein bits for indicating timing further comprises a set of bits for indicating system frame number (SFN), part of the set of bits for indicating the SFN are placed in positions indicated by sequence numbers of 6, 10, 30, 8, 17, 18, and 23 in the first interleaved sequence.

27. The non-transitory computer readable medium according to claim 23, wherein the program codes comprise instructions for:

encoding the second interleaved sequence according to an encoding formula, to obtain an encoded bit sequence, wherein a length of the encoded bit sequence is N; and

wherein the encoding formula is;

x₁^N=u₁^NG_N

wherein u₁^N=(u₁, u₂, . . . , u_N) is a binary row vector representing the second interleaved sequence, x₁^N=(x₁, x₂, . . . , x_N) is the encoded sequence, and G_N is a polar code generating matrix of N rows and N columns.