GOA circuit and OLED display device
First Claim
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1. A gate driver on array (GOA) circuit, which comprises:
- a plurality of cascaded GOA devices, with each GOA device comprising;
a scan signal output device and an emitting signal output device electrically connected to the scan signal output device;
for a positive integer n, except the first GOA device, in the n-th GOA device;
the scan signal output device, receiving an m-th clock signal, an (m+1)-th clock signal, and a scan signal of the (n−
1)-th GOA device, for outputting a scan signal of n-th GOA device to sub-pixels of n-th row and the emitting signal output device of the n-th GOA device according to the m-th clock signal under the control of the scan signal of the (n−
1)-th GOA device;
the emitting signal output device, receiving the scan signal outputted by the scan signal output device of the n-th GOA device, for outputting an emitting signal of the n-th GOA device to the sub-pixels of n-th row;
during a frame period, the scan signal of each GOA device comprising at least two low voltage pulses, the emitting signal of each GOA device having a duration of outputting high voltage longer than twice the pulse cycle of the m-th clock signal, and the m-th clock signal and the (m+1)-th clock signal having opposite phases;
wherein the scan signal output device comprises;
a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;
the first TFT having a gate receiving a constant low voltage, a source electrically connected to a drain of the second TFT, and a drain electrically connected to a first node of the n-th GOA device;
the second TFT having a gate and a source, both receiving the scan signal of the (n−
1)-th GOA device;
the third TFT having a gate receiving the constant low voltage, a source electrically connected to the source of the second TFT, and a drain electrically connected to a gate of the fifth TFT;
the fourth TFT having a gate receiving the constant low voltage, a source electrically connected to the first node of the n-th GOA device, and a drain electrically connected to a source of the sixth TFT;
the fifth TFT having a source electrically connected to a second node of the n-th GOA device, and a drain receiving a constant high voltage;
the sixth TFT having a gate electrically connected to the second node of the n-th GOA device, and a drain receiving a constant high voltage;
the seventh TFT having a gate electrically connected to the drain of the third TFT, a source electrically connected to a drain of the eighth TFT, and a drain receiving the constant high voltage;
the eighth TFT having a gate and a source, both receiving the m-th clock signal;
the ninth TFT having a gate receiving the (m+1)-th clock signal, a source electrically connected to a drain of the tenth TFT, and a drain electrically connected to the second node of the n-th GOA device;
the tenth TFT having a gate electrically connected to the drain of the eighth TFT, and a source receiving the (m+1)-th clock signal;
the eleventh TFT having a gate electrically connected to the second node of the GOA device, a source electrically connected to a drain of the twelfth TFT, and a drain receiving the constant high voltage;
the twelfth TFT having a gate electrically connected to the first node of the GOA device, a source receiving the m-th clock signal, and a drain outputting the scan signal of the n-th GOA device;
the first capacitor having a first end electrically connected to the source of the sixth TFT, and a second end receiving the constant high voltage;
the second capacitor having a first end electrically connected to the first node of the GOA device, and a second end electrically connected to the drain of the twelfth TFT;
the third capacitor having a first end electrically connected to the second node of the GOA device, and a second end receiving the constant high voltage;
the fourth capacitor having a first end electrically connected to the drain of the eighth TFT, and a second end receiving the constant high voltage.
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Abstract
The invention provides a GOA circuit and OLED display device. The GOA circuit comprises a plurality of cascaded GOA units, with each GOA unit comprising: a scan signal output module and an emitting signal output module electrically connected to the scan signal output module; during a frame period, the scan signal output module is capable of outputting a scanning signal including at least two low potential pulses within a frame time, and the light emitting signal output module can output a valid emitting signal according to the scan signal outputted by the scan signal output module. Thus, the GOA circuit for scan signal and the GOA circuit for emitting signal in the conventional design are integrated into a GOA circuit, which can reduce the number of TFTs and capacitors, simplify the circuit structure, and facilitate narrow-border display.
7 Citations
11 Claims
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1. A gate driver on array (GOA) circuit, which comprises:
- a plurality of cascaded GOA devices, with each GOA device comprising;
a scan signal output device and an emitting signal output device electrically connected to the scan signal output device;for a positive integer n, except the first GOA device, in the n-th GOA device; the scan signal output device, receiving an m-th clock signal, an (m+1)-th clock signal, and a scan signal of the (n−
1)-th GOA device, for outputting a scan signal of n-th GOA device to sub-pixels of n-th row and the emitting signal output device of the n-th GOA device according to the m-th clock signal under the control of the scan signal of the (n−
1)-th GOA device;the emitting signal output device, receiving the scan signal outputted by the scan signal output device of the n-th GOA device, for outputting an emitting signal of the n-th GOA device to the sub-pixels of n-th row; during a frame period, the scan signal of each GOA device comprising at least two low voltage pulses, the emitting signal of each GOA device having a duration of outputting high voltage longer than twice the pulse cycle of the m-th clock signal, and the m-th clock signal and the (m+1)-th clock signal having opposite phases; wherein the scan signal output device comprises;
a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;the first TFT having a gate receiving a constant low voltage, a source electrically connected to a drain of the second TFT, and a drain electrically connected to a first node of the n-th GOA device; the second TFT having a gate and a source, both receiving the scan signal of the (n−
1)-th GOA device;the third TFT having a gate receiving the constant low voltage, a source electrically connected to the source of the second TFT, and a drain electrically connected to a gate of the fifth TFT; the fourth TFT having a gate receiving the constant low voltage, a source electrically connected to the first node of the n-th GOA device, and a drain electrically connected to a source of the sixth TFT; the fifth TFT having a source electrically connected to a second node of the n-th GOA device, and a drain receiving a constant high voltage; the sixth TFT having a gate electrically connected to the second node of the n-th GOA device, and a drain receiving a constant high voltage; the seventh TFT having a gate electrically connected to the drain of the third TFT, a source electrically connected to a drain of the eighth TFT, and a drain receiving the constant high voltage; the eighth TFT having a gate and a source, both receiving the m-th clock signal; the ninth TFT having a gate receiving the (m+1)-th clock signal, a source electrically connected to a drain of the tenth TFT, and a drain electrically connected to the second node of the n-th GOA device; the tenth TFT having a gate electrically connected to the drain of the eighth TFT, and a source receiving the (m+1)-th clock signal; the eleventh TFT having a gate electrically connected to the second node of the GOA device, a source electrically connected to a drain of the twelfth TFT, and a drain receiving the constant high voltage; the twelfth TFT having a gate electrically connected to the first node of the GOA device, a source receiving the m-th clock signal, and a drain outputting the scan signal of the n-th GOA device; the first capacitor having a first end electrically connected to the source of the sixth TFT, and a second end receiving the constant high voltage; the second capacitor having a first end electrically connected to the first node of the GOA device, and a second end electrically connected to the drain of the twelfth TFT; the third capacitor having a first end electrically connected to the second node of the GOA device, and a second end receiving the constant high voltage; the fourth capacitor having a first end electrically connected to the drain of the eighth TFT, and a second end receiving the constant high voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- a plurality of cascaded GOA devices, with each GOA device comprising;
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9. A gate driver on array (GOA) circuit, which comprises:
- a plurality of cascaded GOA devices, with each GOA device comprising;
a scan signal output device and an emitting signal output device electrically connected to the scan signal output device;for a positive integer n, except the first GOA device, in the n-th GOA device; the scan signal output device, receiving an m-th clock signal, an (m+1)-th clock signal, and a scan signal of the (n−
1)-th GOA device, for outputting a scan signal of n-th GOA device to sub-pixels of n-th row and the emitting signal output device of the n-th GOA device according to the m-th clock signal under the control of the scan signal of the (n−
1)-th GOA device;the emitting signal output device, receiving the scan signal outputted by the scan signal output device of the n-th GOA device, for outputting an emitting signal of the n-th GOA device to the sub-pixels of n-th row; during a frame period, the scan signal of each GOA device comprising at least two low voltage pulses, the emitting signal of each GOA device having a duration of outputting high voltage longer than twice the pulse cycle of the m-th clock signal, and the m-th clock signal and the (m+1)-th clock signal having opposite phases; wherein the scan signal output device comprising;
a first thin film transistor (TFT), a second TFT, a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a tenth TFT, an eleventh TFT, a twelfth TFT, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;the first TFT having a gate receiving a constant low voltage, a source electrically connected to a drain of the second TFT, and a drain electrically connected to a first node of the n-th GOA unit device; the second TFT having a gate and a source, both receiving the scan signal of the (n−
1)-th GOA device;the third TFT having a gate receiving the constant low voltage, a source electrically connected to the source of the second TFT, and a drain electrically connected to a gate of the fifth TFT; the fourth TFT having a gate receiving the constant low voltage, a source electrically connected to the first node of the n-th GOA device, and a drain electrically connected to a source of the sixth TFT; the fifth TFT having a source electrically connected to a second node of the n-th GOA device, and a drain receiving a constant high voltage; the sixth TFT having a gate electrically connected to the second node of the n-th GOA device, and a drain receiving a constant high voltage; the seventh TFT having a gate electrically connected to the drain of the third TFT, a source electrically connected to a drain of the eighth TFT, and a drain receiving the constant high voltage; the eighth TFT having a gate and a source, both receiving the m-th clock signal; the ninth TFT having a gate receiving the (m+1)-th clock signal, a source electrically connected to a drain of the tenth TFT, and a drain electrically connected to the second node of the n-th GOA device; the tenth TFT having a gate electrically connected to the drain of the eighth TFT, and a source receiving the (m+1)-th clock signal; the eleventh TFT having a gate electrically connected to the second node of the GOA device, a source electrically connected to a drain of the twelfth TFT, and a drain receiving the constant high voltage; the twelfth TFT having a gate electrically connected to the first node of the GOA device, a source receiving the m-th clock signal, and a drain outputting the scan signal of the n-th GOA device; the first capacitor having a first end electrically connected to the source of the sixth TFT, and a second end receiving the constant high voltage; the second capacitor having a first end electrically connected to the first node of the GOA device, and a second end electrically connected to the drain of the twelfth TFT; the third capacitor having a first end electrically connected to the second node of the GOA device, and a second end receiving the constant high voltage; the fourth capacitor having a first end electrically connected to the drain of the eighth TFT, and a second end receiving the constant high voltage; wherein the emitting signal output device comprising;
a thirteenth TFT, a fourteenth TFT, a fifteenth TFT, a sixteenth TFT, and a fifth capacitor;the thirteenth TFT having a gate receiving the scan signal of the n-th GOA device, a source receiving the constant high voltage, and a drain electrically connected to a source of the fourteenth TFT; the fourteenth TFT having a gate receiving the emitting signal of the n-th GOA device, and a drain receiving the constant low voltage; the fifteenth TFT having a gate receiving the emitting signal of the n-th GOA device, a source receiving the constant high voltage, and a drain outputting the emitting signal of the n-th GOA device; the sixteenth TFT having a gate electrically connected to the drain of the thirteen TFT, a source electrically connected to the drain of the fifteenth TFT, and a drain receiving the constant low voltage; the fifth capacitor having a first end electrically connected to the drain of the thirteenth TFT, and a second end receiving the m-th clock signal; comprising two clock signals;
a first clock signal and a second clock signal;
when the m-th clock signal being the second clock signal, the (m+1)-th clock signal being the first clock signal;wherein in the first GOA device, both the gate and the source of the second TFT receiving a circuit start signal. - View Dependent Claims (10, 11)
- a plurality of cascaded GOA devices, with each GOA device comprising;
Specification
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Current AssigneeWuhan China Star Optoelectronics Semiconductor Display Technology Ltd.
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Original AssigneeWuhan China Star Optoelectronics Semiconductor Display Technology Ltd.
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InventorsLiu, Jie
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Primary Examiner(s)Mengistu, Amare
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Assistant Examiner(s)Nadkarni, Sarvesh J
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Application NumberUS15/767,816Publication NumberTime in Patent Office869 DaysField of SearchNoneUS Class CurrentCPC Class CodesG09G 2300/0408 Integration of the drivers ...G09G 2300/0861 with additional control of ...G09G 2310/0286 Details of a shift register...G09G 2310/08 Details of timing specific ...G09G 2380/02 Flexible displaysG09G 3/3258 with pixel circuitry contro...G09G 3/3266 Details of drivers for scan...G09G 3/3674 Details of drivers for scan...
