Semicondcutor package and manufacturing method of semicondcutor package

• US 10,720,399 B2
• Filed: 10/25/2018
• Issued: 07/21/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Fang-Yu, Yang, Ching-Feng, Wu, Kai-Chiang
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US16/171,335
• Publication Number:
  US 20200135669A1
• Time in Patent Office: 635 Days
• Field of Search: 438701
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31127 Etching organic layers
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/6672 for integrated passive components, e.g. semiconductor device with passive components only integrated circuits with passive components only per se H01L27/01
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/24265 : the item being a discrete passive component
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32237 : the layer connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/40 : Radiating elements coated with or embedded in protective material

Abstract

A semiconductor package includes an encapsulated semiconductor device, a first redistribution structure, an insulating layer, and an antenna. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure is disposed on a first side the encapsulated semiconductor device and electrically connected to the semiconductor device. The insulating layer is disposed on a second side of the encapsulated semiconductor device and comprises a groove pattern. The antenna is filled the groove pattern, wherein an upper surface of the antenna is substantially coplanar with an upper surface of the insulating layer.

Claims

1. A manufacturing method of a semiconductor package, comprising:

forming an encapsulated semiconductor device on a carrier;

forming a first redistribution structure on a first side of the encapsulated semiconductor device;

removing the carrier from the encapsulated semiconductor device;

forming an insulating layer on a second side of the encapsulated semiconductor device where the carrier is removed from;

forming a groove pattern on the insulating layer;

filling a conductive paste in the groove pattern; and

performing a curing process on the conductive paste to form an antenna in the groove pattern, wherein an upper surface of the antenna is substantially coplanar with an upper surface of the insulating layer.

2. The manufacturing method of the semiconductor package as claimed in claim 1, further comprising:

forming a second redistribution structure on the carrier before the encapsulated semiconductor device is formed on the carrier, wherein the insulating layer is formed on the second redistribution structure on the second side of the encapsulated semiconductor device.

3. The manufacturing method of the semiconductor package as claimed in claim 1, wherein the groove pattern is formed by laser drilling.

4. The manufacturing method of the semiconductor package as claimed in claim 1, further comprising:

performing a planarizing process on the antenna and the insulating layer after the conductive paste is cured.

5. The manufacturing method of the semiconductor package as claimed in claim 1, further comprising:

forming a protection layer on the insulating layer to cover the upper surface of the antenna and the upper surface of the insulating layer.

6. A method, comprising:

placing a semiconductor device on a first-side redistribution structure;

encapsulating the semiconductor device with an encapsulating material placed on the first-side redistribution structure;

forming a second-side redistribution structure on the encapsulating material and the semiconductor device encapsulated by the encapsulating material;

after forming the second-side redistribution structure, forming an insulating layer on the first-side redistribution structure;

forming a groove pattern on the insulating layer; and

filling a conductive paste in the groove pattern and curing the conductive paste to form an antenna in the groove pattern.

7. The method as claimed in claim 6, wherein an active surface of the semiconductor device faces the first-side redistribution structure after the semiconductor device is placed on the first-side redistribution structure.

8. The method as claimed in claim 6, wherein a back surface of the semiconductor device faces the first-side redistribution structure after the semiconductor device is placed on the first-side redistribution structure.

9. The method as claimed in claim 6, wherein the groove pattern is formed by laser drilling and the groove pattern comprises tapered sidewalls.

10. The method as claimed in claim 6, further comprising:

after curing the conductive paste, performing a planarizing process on the antenna and the insulating layer, wherein an upper surface of the antenna is substantially coplanar with an upper surface of the insulating layer after performing the planarizing process on the antenna and the insulating layer.

11. The method as claimed in claim 6, further comprising:

forming a protection layer on the insulating layer to cover the upper surface of the antenna and the upper surface of the insulating layer.

12. The method as claimed in claim 6, further comprising:

forming through vias on the first-side redistribution structure before encapsulating the semiconductor device with the encapsulating material,

wherein the second-side redistribution structure is electrically connected to the first-side redistribution structure through the through vias encapsulated by the encapsulating material.

13. The method as claimed in claim 6, wherein the conductive paste is filled in the groove pattern without using a mask or a stencil.

14. The method as claimed in claim 6, wherein the conductive paste is filled in the groove pattern without using a screen printing process.

15. A method, comprising:

providing an encapsulated semiconductor device comprising a first-side redistribution structure and a second second-side redistribution structure disposed on opposite sides thereof;

forming an insulating layer covering the first-side redistribution structure;

forming a groove pattern on the insulating layer;

filling a conductive paste in the groove pattern such that slope of tapered sidewalls of the conductive paste is controlled by the groove pattern; and

curing the conductive paste filled in the groove pattern.

16. The method as claimed in claim 15, wherein the conductive paste is filled in the groove pattern without using a mask or a stencil.

17. The method as claimed in claim 15, wherein the conductive paste is filled in the groove pattern without using a screen printing process.

18. The method as claimed in claim 15, wherein the groove pattern is formed by laser drilling.

19. The method as claimed in claim 15, further comprising:

after curing the conductive paste, performing a planarizing process on the conductive paste.

20. The method as claimed in claim 15, further comprising:

forming a protection layer to cover an upper surface of the conductive paste.