Microphone assembly with pulse density modulated signal

• US 10,721,557 B2
• Filed: 12/20/2018
• Issued: 07/21/2020
• Est. Priority Date: 02/09/2016
• Status: Active Grant

• Current Assignee: Knowles Electronics Llc (Knowles Corporation)
• Original Assignee: Knowles Electronics Llc (Knowles Corporation)
• Inventors: Pawlowski, Andrzej, Strange, Kasper, Berthelsen, Kim Spetzler, Thomsen, Henrik
• Primary Examiner(s): Tran, Thang V
• Application Number:
  US16/228,580
• Publication Number:
  US 20190124440A1
• Time in Patent Office: 579 Days
• CPC Class Codes: G10L 2021/02163 Only one microphone
• CPC Class Codes: G10L 21/0232 Processing in the frequency domain
• CPC Class Codes: H03M 7/3026 the quantiser being a multiple bit one
• CPC Class Codes: H03M 7/3042 the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
• CPC Class Codes: H04R 1/08 Mouthpieces; Microphones; Attachments therefor
• CPC Class Codes: H04R 19/04 Microphones H04R19/01 takes precedence
• CPC Class Codes: H04R 2201/003 Mems transducers or their use of the electrostatic type H04R19/005
• CPC Class Codes: H04R 2410/03 Reduction of intrinsic noise in microphones
• CPC Class Codes: H04R 3/002 Damping circuit arrangements for transducers, e.g. motional feedback circuits

Abstract

The disclosure relates to a microphone assembly including a multibit analog-to-digital converter configured to generate N-bit samples representative of a microphone signal. The microphone assembly also includes a first digital-to-digital converter configured to generate a corresponding M-bit digital signal based on N-bit digital samples, wherein N and M are positive integers and N>M. The microphone assembly may include a data interface configured to repeatedly receive samples of the M-bit digital signal and write bits of the M-bit digital signal to a data frame.

Claims

1. A microphone assembly comprising:

a transducer configured to convert sound into an electrical signal; and

an electrical circuit comprising;

a multibit analog-to-digital converter coupled to an output of the transducer, the analog-to digital converter configured to generate N-bit digital samples representative of the electrical signal;

a first digital-to-digital converter configured to generate an M-bit digital signal based on the N-bit digital samples, wherein N and M are positive integers and N>

M>

1; and

a processor configured to control performance of the microphone assembly by configuring the first digital-to-digital converter with configuration information stored in a register of the electrical circuit.

2. The assembly of claim 1, further comprising a physical interface comprising a clock contact and a data contact coupled to the electrical circuit.

3. The assembly of claim 2, further comprising:

a second digital-to-digital converter configured to generate a single-bit digital signal based on the N-bit digital samples; and

a multiplexer comprising a first input coupled to an output of the first digital-to-digital converter and a second input coupled to an output of the second digital-to-digital converter;

wherein the multiplexer is configured to selectively transmit either the single-bit digital signal or the M-bit digital signal to the physical interface.

4. The assembly of claim 3, wherein the first digital-to-digital converter comprises a first integrator having an order not more than 2 and the second digital-to-digital converter comprises a second integrator having an order not more than 4.

5. The assembly of claim 1, wherein the first digital-to-digital converter is configured to generate the M-bit digital signal based on a difference between the N-bit digital samples and a feedback signal from an integrator of the first digital-to-digital converter, and wherein the processor is configured to control a latency of the microphone assembly by configuring an order of the first integrator using configuration information stored in the register.

6. The assembly of claim 1, wherein the processor is configured to control a latency and a signal to noise ratio of the microphone assembly by configuring the first digital-to-digital converter using configuration information stored in the register.

7. The assembly of claim 1, wherein the processor is configured to control a signal to noise ratio of the microphone assembly by configuring a number of bits per sample of the M-bit digital signal using configuration information stored in the register.

8. The assembly of claim 1, further comprising a housing defined by a lid and a substrate, wherein the transducer is a microelectromechanical systems (MEMS) device, and wherein the transducer and the electrical circuit are disposed within the housing.

9. An electrical circuit for a microphone assembly, the electrical circuit comprising:

a multibit analog-to-digital converter configured to generate N-bit digital samples representative of an electrical signal, the electrical signal representative of acoustic activity detected by an electro-acoustic transducer; and

a first digital-to-digital converter configured to generate a corresponding M-bit digital signal based on the N-bit digital samples, wherein N and M are positive integers and N>

M,

the first digital-to-digital converter comprising an integrator having an order that is selected to reduce latency of the electrical circuit.

10. The circuit of claim 9, further comprising a processor configured to configure the order of the integrator of the first digital-to-digital converter using configuration information.

11. The circuit of claim 10, further comprising a register storing the configuration information.

12. The circuit of claim 10, further comprising:

a second digital-to-digital converter configured to generate a single-bit digital signal based on the N-bit digital samples; and

a multiplexer comprising a first input coupled to an output of the first digital-to-digital converter and a second input coupled to an output of the second digital-to-digital converter;

wherein the multiplexer is configured to selectively transmit either the single-bit digital signal or the M-bit digital signal in response to an input to the multiplexer.

13. The circuit of claim 12, wherein the integrator of the first digital-to-digital converter comprises a first integrator having an order not more than 2 and the second digital-to-digital converter comprises a second integrator having an order not more than 4.

14. The circuit of claim 10, wherein the processor is configured to optimize a latency and a signal to noise ratio of the M-bit digital signal by configuring the first digital-to-digital converter with the configuration information stored in the register.

15. The circuit of claim 10, wherein the processor is configured to control a signal to noise ratio of the M-bit digital signal by configuring a sample size of the M-bit digital signal using the configuration information stored in the register.

16. A method in a microphone assembly comprising a transducer and an electrical circuit, the method comprising:

converting sound into an electrical signal using the transducer;

generating N-bit digital samples representative of the electrical signal;

generating an M-bit digital signal by quantizing and noise-shaping the N-bit digital samples, wherein N and M are positive integers and N>

M;

controlling performance of the microphone assembly by configuring a first digital-to-digital converter with configuration information read from a register of the microphone assembly; and

providing an output signal based on the M-bit digital signal.

17. The method of claim 16, further comprising at least one of:

controlling a latency by configuring an order of an integrator with configuration information read from the register; and

controlling a latency and a signal to noise ratio of the M-bit digital signal by configuring the first digital-to-digital converter with configuration information read from the register.

18. The method of claim 16, further comprising controlling a signal to noise ratio of the M-bit digital signal by configuring a sample size of the M-bit digital signal using configuration information read from the register.

19. The method of claim 16, further comprising:

generating a single-bit digital signal by quantizing and noise-shaping the N-bit digital samples; and

selectively providing either the M-bit digital signal or the single-bit digital signal as the output signal.