Digital signal routing circuit
First Claim
1. A digital routing core, comprising:
- a plurality of digital signal processing blocks, wherein each of said digital signal processing blocks comprises a source port and a destination port, said digital signal processing blocks each being configurable to;
receive streams of audio data samples at a respective sample clock rate at said destination port, process the received streams of audio data samples, and transmit the processed streams of audio data samples at said respective sample clock rate from said source port;
a clock generator configurable to generate at least a data clock; and
a router, comprising a router input and a router output, and being configurable to route audio data samples from the router input to the router output in response to said data clock;
a source selector comprising a plurality of source selector inputs and a source selector output, wherein the source selector inputs are configured to receive data from source ports, wherein the source selector output is connected to said router input, and wherein said source selector is configurable in response to a source selector control signal to couple any of said source ports to said router input;
a destination selector comprising a destination selector input and a plurality of destination selector outputs, wherein the destination selector input is connected to said router output, wherein the destination selector outputs are connected to said destination ports, and wherein the destination selector is configurable in response to a destination selector control signal to couple any one of said destination ports to said router output;
programmable storage circuitry configurable to store a plurality of configuration data sets, each one of said plurality of configuration data sets respectively defining a signal path and a respective data sample rate for the signal path, said signal path comprising a source port and a destination port, and the data sample rates of said signal paths being definable independently of each other; and
a controller coupled to said programmable storage circuitry, said source selector and said destination selector, said controller being configured to receive said plurality of configuration data sets and to control said source and destination selectors with respective source and destination selector control signals to establish on a time-division-multiplexed basis in response to said data clock each one of said defined signal paths within each period of a respective sample clock.
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Accused Products
Abstract
An integrated circuit for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44.ikHz or 48 kHz.
34 Citations
20 Claims
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1. A digital routing core, comprising:
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a plurality of digital signal processing blocks, wherein each of said digital signal processing blocks comprises a source port and a destination port, said digital signal processing blocks each being configurable to;
receive streams of audio data samples at a respective sample clock rate at said destination port, process the received streams of audio data samples, and transmit the processed streams of audio data samples at said respective sample clock rate from said source port;a clock generator configurable to generate at least a data clock; and a router, comprising a router input and a router output, and being configurable to route audio data samples from the router input to the router output in response to said data clock; a source selector comprising a plurality of source selector inputs and a source selector output, wherein the source selector inputs are configured to receive data from source ports, wherein the source selector output is connected to said router input, and wherein said source selector is configurable in response to a source selector control signal to couple any of said source ports to said router input; a destination selector comprising a destination selector input and a plurality of destination selector outputs, wherein the destination selector input is connected to said router output, wherein the destination selector outputs are connected to said destination ports, and wherein the destination selector is configurable in response to a destination selector control signal to couple any one of said destination ports to said router output; programmable storage circuitry configurable to store a plurality of configuration data sets, each one of said plurality of configuration data sets respectively defining a signal path and a respective data sample rate for the signal path, said signal path comprising a source port and a destination port, and the data sample rates of said signal paths being definable independently of each other; and a controller coupled to said programmable storage circuitry, said source selector and said destination selector, said controller being configured to receive said plurality of configuration data sets and to control said source and destination selectors with respective source and destination selector control signals to establish on a time-division-multiplexed basis in response to said data clock each one of said defined signal paths within each period of a respective sample clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification