Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates

• US 10,741,264 B2
• Filed: 11/21/2017
• Issued: 08/11/2020
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Primary Examiner(s): Leboeuf, Jerome
• Application Number:
  US15/820,337
• Publication Number:
  US 20180090219A1
• Time in Patent Office: 994 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface and having circuitry formed therein or thereon;

an insulation layer over the semiconductor substrate;

a first active strip and a second active strip formed over the insulating layer, each extending along a first direction substantially parallel to the planar surface and separated from each other by a predetermined distance along a second direction that is also substantially parallel to the planar surface, wherein each active strip comprises (i) a first semiconductor layer of a first conductivity type;

(ii) second and third semiconductor layers on opposite sides of the first semiconductor layer each of a second conductivity type opposite the first conductivity type; and

(iii) a metal layer adjacent and in direct electrical contact with the second semiconductor layer;

a charge-trapping material provided on sidewalls of both the first active strip and the second active strip; and

a plurality of local word line conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being spaced by the charge-trapping material from the first active strip or the second active strip, thereby forming a NOR string along the first direction of each active strip, each NOR string including a plurality of storage transistors that are formed out of the active strip, the second and the third semiconductor layers of the active strip, the charge-trapping material and the local word lines conductors along the side of the active strip.

2. The memory structure of claim 1, wherein each active strip further comprises a dielectric material, which is selected from a group consisting of:

silicon oxide, silicon nitride and an air gap.

3. The memory structure of claim 1, wherein the second and the third semiconductor layers are connected by interconnects to the circuitry on or in the semiconductor substrate.

4. The memory structure of claim 1, wherein the second and the third semiconductor layers are connected by buried contacts to the circuitry on or in the semiconductor substrate.

5. The memory structure of claim 1, wherein each NOR string is associated with at least one pre-charge device on the active strip that pre-charges the second semiconductor layer to a predetermined voltage that is substantially held by a parasitic capacitance along the second semiconductor layer during a program, program-inhibit, reading or erasing operation on the NOR string.

6. The memory structure of claim 5, further comprising circuitry formed in and on the semiconductor surface and wherein the pre-charge device comprises at least one selected storage transistor and wherein the circuitry applies the predetermined voltage to pre-charge the parasitic capacitance, the predetermined voltage being determined according to whether the program, the program-inhibit, the reading or the erasing operation is carried out.

7. The memory structure of claim 5, wherein the pre-charge device comprises one or more pre-charge transistors having a different configuration than the storage transistors in the NOR string.

8. The memory structure of claim 5, wherein the second semiconductor layer serves as a shared virtual ground reference and the third semiconductor layer serves as a common bit line for the storage transistors in each NOR string.

9. The memory structure of claim 1, wherein charge stored in the charge-trapping material in each storage transistor represent data stored in the storage transistor, wherein circuitry is formed on and in the semiconductor substrate that comprises voltage sources for selectively imposing a predetermined voltage configuration on each storage transistor to effectuate programming, program-inhibiting, reading or erasing data stored in the storage transistor.

10. The memory structure of claim 9, wherein said data represents more than one bit of binary information stored on each storage element.

11. The memory structure of claim 9, wherein said data represents a continuum of stored states in an analog memory.

12. The memory structure of claim 9, wherein the circuitry further comprises one or more sense amplifiers for sensing the data stored in the storage transistors of each NOR string.

13. The memory structure of claim 9 wherein, during a read or a program operation, only the local word line conductor associated with an addressed storage transistor of a NOR string is raised for a period of time to a predetermined gate voltage required for the read or the program operation, with the local word line conductors associated with all other storage transistors of the NOR string or pre-charge transistors of the NOR string held at a voltage below a threshold voltage of an erased storage transistor.

14. The memory structure of claim 13, wherein while a storage transistor is being addressed for programming or erase in the first active strip, the second or third semiconductor layer of the second active strip is floated or pre-charged to an inhibit voltage.

15. The memory structure of claim 13, wherein storage transistors associated with the active strips are programmed in a single concurrent programming operation.

16. The memory structure of claim 15 wherein, during the concurrent programming operation, the second semiconductor layer of each active strip in each plane is appropriately pre-charged to the selected predetermined voltage associated with a program or a program-inhibit operation, programming voltage pulses are then applied to one or more addressed local word line conductors, and wherein the concurrent programming operation is terminated after all storage transistors associated with the addressed local word line conductors are read-verified to have reached their respective intended programmed states.

17. The memory structure of claim 16, wherein the programming voltage is one of several programming voltages in a programming sequence, the programming voltages representing different data values.