Semiconductor device with integrated capacitor and manufacturing method thereof

• US 10,741,488 B2
• Filed: 02/21/2018
• Issued: 08/11/2020
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Chung-Yen
• Primary Examiner(s): Sayadian, Hrayr A
• Application Number:
  US15/901,342
• Publication Number:
  US 20190103352A1
• Time in Patent Office: 902 Days
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A semiconductor structure includes a capacitor including a first electrode and a second electrode disposed over and electrically insulated from the first electrode. The semiconductor structure also includes a first conductive via extending through the first electrode and contacting a planar surface of the first electrode. The semiconductor structure further includes a second conductive via extending through the second electrode and contacting a planar surface of the second electrode.

Claims

1. A semiconductor structure, comprising:

a capacitor comprising a first conductive plate, a second conductive plate and a third conductive plate, the second conductive plate electrically insulated from the first conductive plate and the third conductive plate, and each of the first conductive plate, the second conductive plate and the third conductive plate comprising a planar surface;

a first conductive via extending through the first conductive plate and the third conductive plate, and contacting the planar surface of the first conductive plate and the planar surface of the third conductive plate;

a second conductive via extending through the second conductive plate and contacting the planar surface of the second conductive plate; and

a conductive line below the first conductive plate, wherein the conductive line comprises an upper surface, wherein the first conductive via terminates on the upper surface of the conductive line.

2. The semiconductor structure according to claim 1, further comprising a dielectric layer electrically insulating the first conductive plate from the second conductive plate.

3. The semiconductor structure according to claim 1, wherein each of the first conductive via and the second conductive via comprises a stepped shape having a top portion and a bottom portion in which the top portion is wider than the bottom portion.

4. The semiconductor structure according to claim 1, wherein at least one of the first conductive plate and the second conductive plate comprises an angled sidewall.

5. The semiconductor structure according to claim 1, further comprising an insulating film electrically insulating the second conductive plate from the first and the third conductive plates, wherein the insulating film comprises a first portion, wherein the first portion contacts the first conductive plate and separates the first conductive via from the second conductive plate.

6. The semiconductor structure according to claim 5, wherein the first conductive plate comprises a second portion exposed through the first portion of the insulating film, and the insulating film covers an entirety of the second conductive plate.

7. The semiconductor structure according to claim 5, wherein the first conductive via and the second conductive via extend through the insulating film.

8. A semiconductor structure, comprising:

a semiconductor substrate; and

a redistribution layer disposed over and electrically coupled to the semiconductor substrate, the redistribution layer comprising;

a first conductive line and a second conductive line; and

a capacitor over the first conductive line and the second conductive line, the capacitor comprising;

a first conductive plate;

a first insulating film over the first conductive plate;

a second conductive plate adjacent to the first conductive plate and electrically insulated from the first conductive plate by the first insulating film;

a second insulating film over the second conductive plate;

a third conductive plate over the second conductive plate and electrically insulated from the second conductive plate by the second insulating film, wherein each of the first conductive plate, the second conductive plate and the third conductive plate comprises a planar surface;

a first conductive via extending through the first conductive plate and the third conductive plate, the first conductive via terminating on the first conductive line and contacting the planar surface of the first conductive plate and the planar surface of the third conductive plate; and

a second conductive via extending through the second insulating film, the second conductive via terminating on the second conductive line and contacting the planar surface of the second conductive plate.